Abstract: A device and a method for training a model are disclosed, wherein the method of training the model includes: first classifying a plurality of data packets using the model, wherein a first class is assigned to each data packet of a plurality of data packets, wherein the first class is associated with a receiver of a plurality of receivers; second classifying the plurality of data packets, wherein a second class is assigned to each data packet of the plurality of data packets, wherein the second class is associated with a receiver of the plurality of receivers; and training the model using the plurality of first classes and the plurality of second classes assigned to the plurality of data packets.

Abstract: A device and a method for training a model are disclosed, wherein the method of training the model includes: first classifying a plurality of data packets using the model, wherein a first class is assigned to each data packet of a plurality of data packets, wherein the first class is associated with a receiver of a plurality of receivers; second classifying the plurality of data packets, wherein a second class is assigned to each data packet of the plurality of data packets, wherein the second class is associated with a receiver of the plurality of receivers; and training the model using the plurality of first classes and the plurality of second classes assigned to the plurality of data packets.

Abstract: In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.

Abstract: In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.