Patents by Inventor Emil Zak

Emil Zak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10176187
    Abstract: A method for generating a plurality of indexed data fields based on a pattern set comprising a plurality of patterns, the method comprising detecting for each pattern from the pattern set a pattern offset; creating for each pattern offset in the pattern set an indexed pattern group, wherein the index of the indexed pattern group corresponds to the pattern offset; adding each pattern in the pattern set having the same pattern offset to the indexed pattern group having an index corresponding to the pattern offset; adding each pattern having no specific pattern offset to each of the indexed pattern groups; and compiling each indexed pattern group into an indexed data field.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: January 8, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Emil Zak, Biao Liang
  • Patent number: 10135851
    Abstract: The invention relates to a method for pattern processing on a processor platform, the method comprising: compiling a plurality of patterns into a plurality of data structures using the first processing unit, wherein the compiling is such that at least head data parts of the plurality of data structures fit into local memories of computation units of a second processing unit; and uploading the plurality of data structures into the second processing unit such that at least the head data parts of the plurality of data structures are uploaded into the local memories of the computation units of the second processing unit and remaining data parts of the plurality of data structures not fitting into the local memories are uploaded into a global memory of the second processing unit.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: November 20, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Emil Zak, Biao Liang
  • Publication number: 20160344759
    Abstract: The invention relates to a method for pattern processing on a processor platform, the method comprising: compiling a plurality of patterns into a plurality of data structures using the first processing unit, wherein the compiling is such that at least head data parts of the plurality of data structures fit into local memories of computation units of a second processing unit; and uploading the plurality of data structures into the second processing unit such that at least the head data parts of the plurality of data structures are uploaded into the local memories of the computation units of the second processing unit and remaining data parts of the plurality of data structures not fitting into the local memories are uploaded into a global memory of the second processing unit.
    Type: Application
    Filed: January 13, 2014
    Publication date: November 24, 2016
    Inventors: Emil ZAK, Biao LIANG
  • Publication number: 20160321289
    Abstract: A method for generating a plurality of indexed data fields based on a pattern set comprising a plurality of patterns, the method comprising detecting for each pattern from the pattern set a pattern offset; creating for each pattern offset in the pattern set an indexed pattern group, wherein the index of the indexed pattern group corresponds to the pattern offset; adding each pattern in the pattern set having the same pattern offset to the indexed pattern group having an index corresponding to the pattern offset; adding each pattern having no specific pattern offset to each of the indexed pattern groups; and compiling each indexed pattern group into an indexed data field.
    Type: Application
    Filed: July 13, 2016
    Publication date: November 3, 2016
    Inventors: Emil Zak, Biao Liang
  • Publication number: 20160119198
    Abstract: A deep packet inspection method and device, and a coprocessor. The deep packet inspection method includes receiving, by a transceiver module of the coprocessor, an original data packet sent by a general processor, and sending the original data packet to a processor core of the coprocessor; invoking, by the processor core, a sub-coprocessor of the coprocessor to perform application layer parsing on the original data packet so as to obtain an application layer parsing result; and sending, by the processor core, the parsing result to the general processor so that the general processor processes the original data packet according to the parsing result. The deep packet inspection method and device provided by the embodiments of the present disclosure reduce resource occupation of a general processor and increase a running speed.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 28, 2016
    Inventors: Aviv Kfir, Daniel Moscovici, Emil Zak, Mo Mo
  • Publication number: 20070071233
    Abstract: A hash unit, including an input interface adapted to receive an input key, an arbitrary number generator adapted to generate one or more arbitrary numbers, a processor adapted to apply a multi-operand function to an input key received by the input interface together with each of one or more arbitrary numbers generated by the generator so as to generate intermediate results, to mathematically combine the digits of the intermediate results to generate respective short bit results having less than half the bits of the intermediate results and to concatenate the short bit results and an output unit adapted to provide the concatenated short bit results for use as an output hash key.
    Type: Application
    Filed: September 27, 2005
    Publication date: March 29, 2007
    Applicant: Allot Communications Ltd.
    Inventor: Emil Zak