Patents by Inventor Emile Davies-Venn
Emile Davies-Venn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11295998Abstract: Techniques for fabricating a package substrate and/or a stiffener for a semiconductor package are described. For one technique, a package substrate comprises: a routing layer comprising a dielectric layer. A stiffener may be above the routing layer and a conductive line may be on the routing layer, the conductive line comprising first and second portions, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region. One or more portions of the conductive line can be perpendicular to an edge of the stiffener. The perpendicular portion(s) may comprise a transition between the first and second widths.Type: GrantFiled: April 4, 2018Date of Patent: April 5, 2022Assignee: Intel CorporationInventors: Stephen Christianson, Stephen Hall, Emile Davies-Venn, Dong-Ho Han, Kemal Aygun, Konika Ganguly, Jun Liao, M. Reza Zamani, Cory Mason, Kirankumar Kamisetty
-
Patent number: 10910314Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.Type: GrantFiled: December 12, 2019Date of Patent: February 2, 2021Assignee: Intel CorporationInventors: Li-Sheng Weng, Chung-Hao Joseph Chen, Emile Davies-Venn, Kemal Aygun, Mitul B. Modi
-
Publication number: 20200118930Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.Type: ApplicationFiled: December 12, 2019Publication date: April 16, 2020Inventors: Li-Sheng Weng, Chung-Hao Joseph Chen, Emile Davies-Venn, Kemal Aygun, Mitul B. Modi
-
Patent number: 10510667Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.Type: GrantFiled: December 21, 2016Date of Patent: December 17, 2019Assignee: Intel CorporationInventors: Li-Sheng Weng, Chung-Hao Joseph Chen, Emile Davies-Venn, Kemal Aygun, Mitul B. Modi
-
Publication number: 20190311963Abstract: Techniques for fabricating a package substrate and/or a stiffener for a semiconductor package are described. For one technique, a package substrate comprises: a routing layer comprising a dielectric layer. A stiffener may be above the routing layer and a conductive line may be on the routing layer, the conductive line comprising first and second portions, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region. One or more portions of the conductive line can be perpendicular to an edge of the stiffener. The perpendicular portion(s) may comprise a transition between the first and second widths.Type: ApplicationFiled: April 4, 2018Publication date: October 10, 2019Inventors: Stephen CHRISTIANSON, Stephen HALL, Emile DAVIES-VENN, Dong-Ho HAN, Kemal AYGUN, Konika GANGULY, Jun LIAO, M. Reza ZAMANI, Cory MASON, Kirankumar KAMISETTY
-
Publication number: 20180174972Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.Type: ApplicationFiled: December 21, 2016Publication date: June 21, 2018Inventors: Li-Sheng Weng, Chung-Hao Joseph Chen, Emile Davies-Venn, Kemal Aygun, Mitul B. Modi
-
Patent number: 9520350Abstract: Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via.Type: GrantFiled: March 13, 2013Date of Patent: December 13, 2016Assignee: Intel CorporationInventors: Weng Hong Teh, Emile Davies-Venn, Ebrahim Andideh, Digvijay A. Raorane, Daniel N. Sobieski
-
Publication number: 20140264830Abstract: Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Inventors: Weng Hong Teh, Emile Davies-Venn, Ebrahim Andideh, Digvijay A. Raorane, Daniel N. Sobieski
-
Patent number: 8804366Abstract: A microelectronic package having a radio frequency (RF) amplifier circuit and, incorporating harmonic rejection filters and matching circuits integrally formed in the package is disclosed. A harmonic rejection filter may comprise a metal-insulator-metal (MIM) capacitor serially coupled between bond pads disposed on a RF amplifier circuit die, a first wire bond coupling a first bond pad to a package output, where the first bond pad is coupled to the output of the RF amplifier, and a second wire bond coupling a second bond pad to a package ground. The harmonic rejection filter may be appropriately configured to filter one or more harmonics at different frequencies.Type: GrantFiled: December 12, 2011Date of Patent: August 12, 2014Assignee: Intel CorporationInventors: Telesphor Kamgaing, Emile Davies-Venn
-
Publication number: 20120092076Abstract: A microelectronic package having a radio frequency (RF) amplifier circuit and, incorporating harmonic rejection filters and matching circuits integrally formed in the package is disclosed. A harmonic rejection filter may comprise a metal-insulator-metal (MIM) capacitor serially coupled between bond pads disposed on a RF amplifier circuit die, a first wire bond coupling a first bond pad to a package output, where the first bond pad is coupled to the output of the RF amplifier, and a second wire bond coupling a second bond pad to a package ground. The harmonic rejection filter may be appropriately configured to filter one or more harmonics at different frequencies.Type: ApplicationFiled: December 12, 2011Publication date: April 19, 2012Inventors: Telesphor Kamgaing, Emile Davies-Venn
-
Patent number: 8111521Abstract: A microelectronic package having a radio frequency (RF) amplifier circuit and, incorporating harmonic rejection filters and matching circuits integrally formed in the package is disclosed. A harmonic rejection filter may comprise a metal-insulator-metal (MIM) capacitor serially coupled between bond pads disposed on a RF amplifier circuit die, a first wire bond coupling a first bond pad to a package output, where the first bond pad is coupled to the output of the RF amplifier, and a second wire bond coupling a second bond pad to a package ground. The harmonic rejection filter may be appropriately configured to filter one or more harmonics at different frequencies.Type: GrantFiled: August 8, 2007Date of Patent: February 7, 2012Assignee: Intel CorporationInventors: Telesphor Kamgaing, Emile Davies-Venn
-
Patent number: 7626472Abstract: Methods and apparatus relating to package embedded three dimensional baluns are described. In one embodiment, components of one or more baluns may be embedded in a single semiconductor substrate. Other embodiments are also described.Type: GrantFiled: March 29, 2007Date of Patent: December 1, 2009Assignee: Intel CorporationInventors: Emile Davies-Venn, Telesphor Kamgaing
-
Publication number: 20090039986Abstract: A microelectronic package having a radio frequency (RF) amplifier circuit and, incorporating harmonic rejection filters and matching circuits integrally formed in the package is disclosed. A harmonic rejection filter may comprise a metal-insulator-metal (MIM) capacitor serially coupled between bond pads disposed on a RF amplifier circuit die, a first wire bond coupling a first bond pad to a package output, where the first bond pad is coupled to the output of the RF amplifier, and a second wire bond coupling a second bond pad to a package ground. The harmonic rejection filter may be appropriately configured to filter one or more harmonics at different frequencies.Type: ApplicationFiled: August 8, 2007Publication date: February 12, 2009Inventors: Telesphor Kamgaing, Emile Davies-Venn
-
Publication number: 20080238568Abstract: Methods and apparatus relating to package embedded three dimensional baluns are described. In one embodiment, components of one or more baluns may be embedded in a single semiconductor substrate. Other embodiments are also described.Type: ApplicationFiled: March 29, 2007Publication date: October 2, 2008Inventors: Emile Davies-venn, Telesphor Kamgaing