Abstract: A method and device for unlatching a door from a frame, using a keyless door latch system, is provided. In one embodiment, a secondary unlocking component receives a signal and derives power from the signal to provide a power source for the keyless door latch system. A microcontroller generates a control signal and an actuator, in response to receiving the control signal, actuates the secondary unlocking component, which allows an energy source, from an exterior of the door, to be transferred to the keyless door latch system for the unlatching of the door.

Abstract: A method and device for unlatching a door from a frame, using a keyless door latch system, is provided. In one embodiment, a secondary unlocking component receives a signal and derives power from the signal to provide a power source for the keyless door latch system. A microcontroller generates a control signal and an actuator, in response to receiving the control signal, actuates the secondary unlocking component, which allows an energy source, from an exterior of the door, to be transferred to the keyless door latch system for the unlatching of the door.

Abstract: A method and device for unlatching a door from a frame, using a keyless door latch system, is provided. In one embodiment, a secondary unlocking component receives a signal and derives power from the signal to provide a power source for the keyless door latch system. A microcontroller generates a control signal and an actuator, in response to receiving the control signal, actuates the secondary unlocking component, which allows an energy source, from an exterior of the door, to be transferred to the keyless door latch system for the unlatching of the door.

Abstract: A method and device for unlatching a door from a frame, using a keyless door latch system, is provided. In one embodiment, a secondary unlocking component receives a signal and derives power from the signal to provide a power source for the keyless door latch system. A microcontroller generates a control signal and an actuator, in response to receiving the control signal, actuates the secondary unlocking component, which allows an energy source, from an exterior of the door, to be transferred to the keyless door latch system for the unlatching of the door.

Abstract: A pattern of symbols is generated and sent to a projector, wherein the pattern includes an array of symbols having a given number of symbol columns and symbol rows, and an image is obtained from a camera. Next the image is decoded in order to generate a decoded pattern of symbols and the depth map is generated as a function of the pattern and the decoded pattern. The image is decoded by placing an array of classification windows on the image and determining the displacement of each classification window in order to optimize a given cost function. Finally, the decoded pattern is generated by determining a respective symbol for each classification window.

Abstract: An embodiment is a computer-implemented method for detecting a straight line in a digital image comprising a plurality of pixels comprising the steps: detecting an edge in the digital image, generating a first straight line which passes through a first pixel of the detected edge, generating a second straight line which passes through a second pixel of the detected edge, which is different from the first pixel, determining at least two intersections with a boundary of the digital image for each generated straight line, determining a set of two parameter values for each generated straight line based on the respective determined at least two intersections, wherein the set of two parameter values uniquely determines the respective generated straight line, and detecting the straight line in the digital image based on the determined sets of two parameter values.

Abstract: A pattern of symbols is generated and sent to a projector, wherein the pattern includes an array of symbols having a given number of symbol columns and symbol rows, and an image is obtained from a camera. Next the image is decoded in order to generate a decoded pattern of symbols and the depth map is generated as a function of the pattern and the decoded pattern. The image is decoded by placing an array of classification windows on the image and determining the displacement of each classification window in order to optimize a given cost function. Finally, the decoded pattern is generated by determining a respective symbol for each classification window.

Abstract: A GOP-independent dynamic bit-rate controller system includes a user interface to receive one or more input parameters, a bit-rate controller and an encoder. The bit-rate controller regulates a bit-rate of an output bit-stream. The bit-rate controller includes multiple bit-rate modules to determine a bit-estimate and a quantization parameter, and a control module to calculate a convergence period based on the received input parameters and a frame rate. The control module selects a bit rate module based on the convergence period and the encoder generates the output bit-stream using the quantization parameter determined by the bit rate module.

Abstract: An embodiment is a computer-implemented method for detecting a straight line in a digital image comprising a plurality of pixels comprising the steps: detecting an edge in the digital image, generating a first straight line which passes through a first pixel of the detected edge, generating a second straight line which passes through a second pixel of the detected edge, which is different from the first pixel, determining at least two intersections with a boundary of the digital image for each generated straight line, determining a set of two parameter values for each generated straight line based on the respective determined at least two intersections, wherein the set of two parameter values uniquely determines the respective generated straight line, and detecting the straight line in the digital image based on the determined sets of two parameter values.

Abstract: An embodiment of the present disclosure relates to system comprises an encoding device. Said encoding device comprises a compression unit, a quantizer, a bit estimator, a bit rate encoder and a variable length encoder. An embodiment also is a method of encoding. Said method estimates a number of bits to encode a macroblock after compressing the data stream. Then the estimated bit encoded by a bit rate encoder and further quantized by the quantizer to get the final encoded bit stream. The number of bits required to encode a macroblock is estimated after the quantization process and before the encoding process. The macroblock bit estimator estimates the number of bits required to encode a particular macroblock depending on the quantized AC coefficients of that macroblock and the quantized AC coefficients of the neighboring frames normalized at a macroblock level.

Abstract: Rate control algorithms are adapted to cover multiple encoding standards. A rate controller includes an input adaptation interface, a core rate controller, and an output adaptation interface. The input adaptation interface converts rate control input parameters of a target encoding standard to corresponding native control input parameters of the rate controller. The core rate controller is coupled to the output of the input adaptation interface generating output parameters conforming to its native encoding standard. The output adaptation interface is coupled to the output of the core rate controller converting the generated output parameters to equivalent rate control output parameters conforming to the target encoding standard.

Abstract: Systems and methods are for implementing a NSV2SV converter that converts a non-scalable video signal to a scalable video signal. In an implementation, a non-scalable video signal encoded in H.264/AVC standard is decoded and segmented into spatial data and motion data. The spatial data is resized into a desired resolution by down-sampling the spatial data. The motion data is also resized in every layer, except in the top layer, of a scalable video coding (SVC) encoder by using an appropriate measure. Further, the motion data is refined based on the resized spatial data in every layer of the SVC encoder. The refined motion data and the down-sampled spatial data are then transformed and entropy encoded in the SVC standard in every layer. The SVC encoded output from every layer is multiplexed to produce a scalable video signal.

Abstract: An embodiment of a method is disclosed for encoding a digital video signal including a first video sequence and a second video sequence jointly forming a stereo-view digital video signal. The method includes: subjecting the first video sequence to discrete cosine transform, quantization and run-length coding to produce a sequence of blocks of non-zero digital levels representative of the first video sequence, subjecting the second video sequence to discrete cosine transform, quantization, run-length coding and variable length coding to produce digital messages representative of the second video sequence, merging the bits of the digital messages into the sequence of blocks of digital levels by substituting the bits of the digital messages for respective Least Significant Bits of e.g. the last digital level in the blocks representative of the first video sequence to produce an encoded digital video signal representative of the first video sequence and the second video sequence.

Abstract: A method of rendering video frames starting from source frames of a scene acquired using a multi-viewpoint camera system including a Free Viewpoint Video (FVV) synthesizing process.

Abstract: A GOP-independent dynamic bit-rate controller system includes a user interface to receive one or more input parameters, a bit-rate controller and an encoder. The bit-rate controller regulates a bit-rate of an output bit-stream. The bit-rate controller includes multiple bit-rate modules to determine a bit-estimate and a quantization parameter, and a control module to calculate a convergence period based on the received input parameters and a frame rate. The control module selects a bit rate module based on the convergence period and the encoder generates the output bit-stream using the quantization parameter determined by the bit rate module.

Abstract: An embodiment of the present disclosure relates to system comprises an encoding device. Said encoding device comprises a compression unit, a quantizer, a bit estimator, a bit rate encoder and a variable length encoder. An embodiment also is a method of encoding. Said method estimates a number of bits to encode a macroblock after compressing the data stream. Then the estimated bit encoded by a bit rate encoder and further quantized by the quantizer to get the final encoded bit stream. The number of bits required to encode a macroblock is estimated after the quantization process and before the encoding process. The macroblock bit estimator estimates the number of bits required to encode a particular macroblock depending on the quantized AC coefficients of that macroblock and the quantized AC coefficients of the neighboring frames normalized at a macroblock level.

Abstract: Systems and methods are for implementing a NSV2SV converter that converts a non-scalable video signal to a scalable video signal. In an implementation, a non-scalable video signal encoded in H.264/AVC standard is decoded and segmented into spatial data and motion data. The spatial data is resized into a desired resolution by down-sampling the spatial data. The motion data is also resized in every layer, except in the top layer, of a scalable video coding (SVC) encoder by using an appropriate measure. Further, the motion data is refined based on the resized spatial data in every layer of the SVC encoder. The refined motion data and the down-sampled spatial data are then transformed and entropy encoded in the SVC standard in every layer. The SVC encoded output from every layer is multiplexed to produce a scalable video signal.

Abstract: A method of rendering video frames starting from source frames of a scene acquired using a multi-viewpoint camera system including a Free Viewpoint Video (FVV) synthesizing process.

Abstract: Rate control algorithms are adapted to cover multiple encoding standards are described. A rate controller includes an input adaptation interface, a core rate controller, and an output adaptation interface. The input adaptation interface converts rate control input parameters of a target encoding standard to corresponding native control input parameters of the rate controller. The core rate controller is coupled to the output of the input adaptation interface generating output parameters conforming to its native encoding standard. The output adaptation interface is coupled to the output of the core rate controller converting the generated output parameters to equivalent rate control output parameters conforming to the target encoding standard.

Abstract: Digital signals are converted between a first and second format by a conversion process including generating coefficients representing the digital signals. The coefficients may be discrete cosine transform coefficient generated during encoding/transcoding of MPEG signals. The coefficients are subject to quantization by generating a dither signal that is added to the coefficients before quantization to generate a quantized signal. Preferably, each coefficient is first subject to a first quantization in the absence of any dither signal added to generate an undithered quantized coefficient. If the undithered quantized signal is equal to zero the undithered quantized coefficient is taken as the output quantized signal. If the undithered quantized coefficient is different from zero, the dither signal is added and the dithered coefficient thus obtained is subject to quantization to generate the output quantized signal.