Abstract: A method of treatment of an electronic circuit including at a location at least one electrically-conductive test pad having a first exposed surface. The method includes the at least partial etching of the test pad from the first surface, and the forming on the electronic circuit of an interconnection level covering said location and including, on the side opposite to said location, a second planar surface adapted for the performing of a hybrid molecular bonding.

Abstract: A method for transferring at least one chip, from a first support to a second support, includes forming, while the chip is assembled to the first support, an interlayer in the liquid state between, and in contact with, a front face of the chip and an assembly surface of a face of the second support and a solidification of the interlayer. Then, the chip is detached from the first support while maintaining the interlayer in the solid state.

Abstract: The present description relates to a method of manufacturing an electronic circuit (30) comprising: a support (32), an assembly site (31) having a first surface protruding from said support intended to be assembled to an assembly site of another electronic circuit by a self-assembly method; and a peripheral area (39) around said assembly site, the assembly site (31) comprising at least one level, each level comprising conductive pads (34) and insulating posts (380) between the conductive pads, said manufacturing method comprising the forming of said at least one level of the assembly site, such that the edges, in at least one direction (X) of the main plane (XY), of each level of the assembly site and the locations, in the at least one direction (X), of the conductive pads and of the insulating posts of the same level are defined in a same photolithography step of said method.

Abstract: An electronic circuit including a surface intended to be attached to another electronic circuit by hybrid molecular bonding. The electronic circuit includes an electrically-insulating layer exposed on the surface, and, distributed in the electrically-insulating layer, first electrically-conductive bonding pads exposed on a first portion of the surface, the density of the first bonding pads on the first portion of the surface being smaller than 30%, and at least one electrically-conductive test pad, exposed on a second portion of the surface containing a square having a side length greater than 30 ?m. The density of electrically-conductive material of the test pad exposed on the second portion of the surface is in the range from 40% to 80%.

Abstract: A method for transferring at least one chip, from a first support to a second support, includes forming, while the chip is assembled to the first support, an interlayer in the liquid state between, and in contact with, a front face of the chip and an assembly surface of a face of the second support and a solidification of the interlayer. Then, the chip is detached from the first support while maintaining the interlayer in the solid state.

Abstract: A method of treatment of an electronic circuit including at a location at least one electrically-conductive test pad having a first exposed surface. The method includes the at least partial etching of the test pad from the first surface, and the forming on the electronic circuit of an interconnection level covering said location and including, on the side opposite to said location, a second planar surface adapted for the performing of a hybrid molecular bonding.

Abstract: Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.

Abstract: Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.

Abstract: One illustrative integrated circuit product disclosed herein includes a transistor device comprising a T-shaped gate structure positioned above an active region defined in a semiconducting substrate, the T-shaped portion of the gate structure comprising a relatively wider upper portion and a relatively narrower lower portion, and first and second conductive source/drain structures positioned adjacent opposite sidewalls of the T-shaped gate structure. In this example, the product also includes first and second air gaps positioned adjacent opposite sidewall of the T-shaped gate structure, wherein each of the air gaps is positioned between at least the lower portion of one of the sidewalls of the T-shaped gate structure and the adjacent conductive source/drain structure.

Abstract: One illustrative IC product disclosed herein includes a first merged doped source/drain region that includes first and second doped regions and an isolation structure positioned adjacent the first doped region. In this example, the product also includes a contact structure positioned adjacent the isolation structure, wherein the contact structure includes a first portion positioned below an upper surface of the first merged doped source/drain region and a second portion positioned above the upper surface, wherein the first portion physically contacts both the first and second doped regions. The product also includes a layer of insulating material positioned on and in physical contact with a portion of an upper surface of the first portion of the contact structure.

Abstract: One illustrative IC product disclosed herein includes a first merged doped source/drain region that includes first and second doped regions and an isolation structure positioned adjacent the first doped region. In this example, the product also includes a contact structure positioned adjacent the isolation structure, wherein the contact structure includes a first portion positioned below an upper surface of the first merged doped source/drain region and a second portion positioned above the upper surface, wherein the first portion physically contacts both the first and second doped regions. The product also includes a layer of insulating material positioned on and in physical contact with a portion of an upper surface of the first portion of the contact structure.

Abstract: An IC product disclosed herein includes a first merged doped source/drain (MDSD) region having an upper surface, a first side surface and a second side surface that intersect one another at a corner of the first merged doped source/drain region, a second MDSD region and a contact trench in an isolation structure positioned between the first and second MDSD regions. The product also includes a conductive gate structure positioned above at least the second MDSD region and a cross-coupled contact structure that comprises a first portion positioned within the contact trench laterally adjacent to and conductively coupled to at least one of the first side surface and the second side surface, and a second portion that is positioned above and conductively coupled to the upper surface of the MDSD region, wherein the cross-coupled contact structure is conductively coupled to the conductive gate structure.

Abstract: Methods and structures that include a vertical-transport field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A second source/drain region is spaced vertically along the semiconductor fin from the first source/drain region. A gate stack is arranged between the second source/drain region and the first source/drain region. A spacer is formed adjacent to a sidewall of the second source/drain region. A first contact is connected with a top surface of the second source/drain region, a second contact is connected with a top surface of the first source/drain region, and a third contact is connected with a top surface of the gate stack. The spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.

Abstract: Methods and structures that include a vertical-transport field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A second source/drain region is spaced vertically along the semiconductor fin from the first source/drain region. A gate stack is arranged between the second source/drain region and the first source/drain region. A spacer is formed adjacent to a sidewall of the second source/drain region. A first contact is connected with a top surface of the second source/drain region, a second contact is connected with a top surface of the first source/drain region, and a third contact is connected with a top surface of the gate stack. The spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.

Abstract: A method is disclosed wherein a gate, having a gate cap and a sacrificial gate sidewall spacer, is formed adjacent to channel region(s) of a transistor and metal plugs, having plug caps, are formed on source/drain regions. The sacrificial gate sidewall spacer is selectively etched, creating a cavity that exposes sidewalls of the gate and gate cap. Optionally, the sidewalls of the gate cap are etched back to widen the upper portion of the cavity. A dielectric spacer layer is deposited to form an air-gap gate sidewall spacer within the cavity. Since different materials are used for the plug caps, gate cap and dielectric spacer layer, a subsequently formed gate contact opening will be self-aligned to the gate. Thus, a gate contact can be formed over an active region (or close thereto) without risk of gate contact-to-metal plug shorting. A structure formed according to the method is also disclosed.

Abstract: Fabrication of a field-effect transistor is performed on a substrate comprising a film made from first semiconductor material, a gate dielectric covered by a gate electrode, source and drain areas separated by the gate electrode, a protection layer covering gate electrode and source and drain areas, and an access hole to the source area and/or to drain area. Metallic material is deposited in the access hole in contact with the first semiconductor material of the source and/or drain area. An electrically conducting barrier layer that is non-reactive with the first semiconductor material and with the metallic material is deposited before reaction of metallic material with first semiconductor material. Transformation heat treatment of the metallic material with the semiconductor material is performed to form a metallic material having a base formed by the semiconductor material generating a set of stresses on a conduction channel arranged between the source and drain areas.

Abstract: Fabrication of a field-effect transistor is performed on a substrate comprising a film made from first semiconductor material, a gate dielectric covered by a gate electrode, source and drain areas separated by the gate electrode, a protection layer covering gate electrode and source and drain areas, and an access hole to the source area and/or to drain area. Metallic material is deposited in the access hole in contact with the first semiconductor material of the source and/or drain area. An electrically conducting barrier layer that is non-reactive with the first semiconductor material and with the metallic material is deposited before reaction of metallic material with first semiconductor material. Transformation heat treatment of the metallic material with the semiconductor material is performed to form a metallic material having a base formed by the semiconductor material generating a set of stresses on a conduction channel arranged between the source and drain areas.