Patents by Inventor Emilio Camerlenghi
Emilio Camerlenghi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11818893Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.Type: GrantFiled: August 11, 2022Date of Patent: November 14, 2023Inventors: Umberto Maria Meotto, Emilio Camerlenghi, Paolo Tessariol, Luca Laurin
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Publication number: 20230078036Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a negative first voltage level to a control gate of a transistor connected between a first node and a string of series-connected memory cells, increasing a voltage level applied to the first node at a particular rate while increasing the voltage level applied to the control gate of the transistor at the particular rate, and in response to the voltage level applied to the first node reaching a particular voltage level, ceasing increasing the voltage level applied to the first node and ceasing increasing the voltage level applied to the control gate of the transistor.Type: ApplicationFiled: November 16, 2022Publication date: March 16, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Giovanni Maria Paolucci, Paolo Tessariol, Emilio Camerlenghi, Gianpietro Carnevale, Augusto Benvenuti
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Publication number: 20230065142Abstract: Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: October 18, 2022Publication date: March 2, 2023Applicant: Micron Technology, Inc.Inventors: Yoshiaki Fukuzumi, Paolo Tessariol, David H. Wells, Lars P. Heineck, Richard J. Hill, Lifang Xu, Indra V. Chary, Emilio Camerlenghi
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Publication number: 20220392914Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.Type: ApplicationFiled: August 11, 2022Publication date: December 8, 2022Inventors: Umberto Maria Meotto, Emilio Camerlenghi, Paolo Tessariol, Luca Laurin
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Patent number: 11514953Abstract: Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: April 29, 2021Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Yoshiaki Fukuzumi, Paolo Tessariol, David H. Wells, Lars P. Heineck, Richard J. Hill, Lifang Xu, Indra V. Chary, Emilio Camerlenghi
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Patent number: 11514987Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.Type: GrantFiled: April 13, 2021Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Giovanni Maria Paolucci, Paolo Tessariol, Emilio Camerlenghi, Gianpietro Carnevale, Augusto Benvenuti
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Patent number: 11417676Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.Type: GrantFiled: August 24, 2020Date of Patent: August 16, 2022Assignee: Micron Technology, Inc.Inventors: Umberto Maria Meotto, Emilio Camerlenghi, Paolo Tessariol, Luca Laurin
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Patent number: 11309039Abstract: Memories having a controller configured, during a pre-charge portion of a read operation, to apply a sequence of increasing voltage levels concurrently to each access line of a plurality of access lines, wherein each voltage level of the sequence of increasing voltage levels is higher than any previous voltage level of the sequence of increasing voltage levels and lower than any subsequent voltage level of the sequence of increasing voltage levels, and determine a particular voltage level of the sequence of increasing voltage levels corresponding to a point at which all memory cells of the plurality of strings of series-connected memory cells are first deemed to be activated while applying the sequence of increasing voltage levels.Type: GrantFiled: March 16, 2021Date of Patent: April 19, 2022Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Tecla Ghilardi, Tommaso Vali, Emilio Camerlenghi, William C. Filipiak, Andrea D'Alessandro
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Publication number: 20220068317Abstract: Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: April 29, 2021Publication date: March 3, 2022Applicant: Micron Technology, Inc.Inventors: Yoshiaki Fukuzumi, Paolo Tessariol, David H. Wells, Lars P. Heineck, Richard J. Hill, Lifang Xu, Indra V. Chary, Emilio Camerlenghi
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Publication number: 20220059559Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.Type: ApplicationFiled: August 24, 2020Publication date: February 24, 2022Inventors: Umberto Maria Meotto, Emilio Camerlenghi, Paolo Tessariol, Luca Laurin
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Publication number: 20210343640Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.Type: ApplicationFiled: July 13, 2021Publication date: November 4, 2021Applicant: Micron Technology, Inc.Inventors: Vladimir Machkaoutsan, Pieter Blomme, Emilio Camerlenghi, Justin B. Dorhout, Jian Li, Ryan L. Meyer, Paolo Tessariol
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Patent number: 11094627Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.Type: GrantFiled: October 25, 2019Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventors: Vladimir Machkaoutsan, Pieter Blomme, Emilio Camerlenghi, Justin B. Dorhout, Jian Li, Ryan L. Meyer, Paolo Tessariol
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Publication number: 20210233591Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.Type: ApplicationFiled: April 13, 2021Publication date: July 29, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Giovanni Maria Paolucci, Paolo Tessariol, Emilio Camerlenghi, Gianpietro Carnevale, Augusto Benvenuti
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Publication number: 20210202020Abstract: Memories having a controller configured, during a pre-charge portion of a read operation, to apply a sequence of increasing voltage levels concurrently to each access line of a plurality of access lines, wherein each voltage level of the sequence of increasing voltage levels is higher than any previous voltage level of the sequence of increasing voltage levels and lower than any subsequent voltage level of the sequence of increasing voltage levels, and determine a particular voltage level of the sequence of increasing voltage levels corresponding to a point at which all memory cells of the plurality of strings of series-connected memory cells are first deemed to be activated while applying the sequence of increasing voltage levels.Type: ApplicationFiled: March 16, 2021Publication date: July 1, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Tecla Ghilardi, Tommaso Vali, Emilio Camerlenghi, William C. Filipiak, Andrea D'Alessandro
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Patent number: 11011236Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.Type: GrantFiled: August 29, 2019Date of Patent: May 18, 2021Assignee: Micron Technology, Inc.Inventors: Giovanni Maria Paolucci, Paolo Tessariol, Emilio Camerlenghi, Gianpietro Carnevale, Augusto Benvenuti
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Publication number: 20210125919Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.Type: ApplicationFiled: October 25, 2019Publication date: April 29, 2021Applicant: Micron Technology, Inc.Inventors: Vladimir Machkaoutsan, Pieter Blomme, Emilio Camerlenghi, Justin B. Dorhout, Jian Li, Ryan L. Meyer, Paolo Tessariol
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Patent number: 10950316Abstract: Apparatus having plurality of data lines each selectively connected to a respective string of series-connected memory cells, a plurality of registers each configured to indicate a state of a respective data line, and logic configured to indicate when each data line of the plurality of data lines has a particular state might facilitate determination of a pass voltage of a read operation.Type: GrantFiled: August 11, 2020Date of Patent: March 16, 2021Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Tecla Ghilardi, Tommaso Vali, Emilio Camerlenghi, William C. Filipiak, Andrea D'Alessandro
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Publication number: 20210065810Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.Type: ApplicationFiled: August 29, 2019Publication date: March 4, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Giovanni Maria Paolucci, Paolo Tessariol, Emilio Camerlenghi, Gianpietro Carnevale, Augusto Benvenuti
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Publication number: 20200372961Abstract: Apparatus having plurality of data lines each selectively connected to a respective string of series-connected memory cells, a plurality of registers each configured to indicate a state of a respective data line, and logic configured to indicate when each data line of the plurality of data lines has a particular state might facilitate determination of a pass voltage of a read operation.Type: ApplicationFiled: August 11, 2020Publication date: November 26, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Tecla Ghilardi, Tommaso Vali, Emilio Camerlenghi, William C. Filipiak, Andrea D'Alessandro
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Patent number: 10777286Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, ceasing increasing the voltage level applied to each access line of the plurality of access lines in response to the state of each data line of the plurality of data lines having a particular condition, changing a voltage level applied to a particular access line of the plurality of access lines to a particular voltage level, and sensing a state of each data line of a subset of the plurality of data lines while applying the particular voltage level to the particular access line.Type: GrantFiled: February 5, 2019Date of Patent: September 15, 2020Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Tecla Ghilardi, Tommaso Vali, Emilio Camerlenghi, William C. Filipiak, Andrea D'Alessandro