Abstract: The invention relates to a method of automatically shifting from the fabrication of an EPROM cell to the fabrication of a ROM cell, which method is specifically intended for semiconductor electronic circuits having a resident memory and is of the type wherein the structure of at least one memory cell transistor is defined on a semiconductor substrate using photolithographic techniques including an active area and a channel region, the cell being adapted to acquire a logic state selected by the user. Advantageously, the conductivity of the active area is changed to suit the logical contents that the cell is intended to contain.

Abstract: A method for assessing alterations in the dielectric properties of insulating layers on a wafer of semiconductor material induced by plasma treatments. The method includes forming cells of EEPROM type on a wafer with source, drain and control gate surface terminals (pads), subjecting the cells to UV radiation so as to erase them thereby fixing a reference threshold voltage, applying programming voltages of preset value to at least one of the cells and measuring the corresponding threshold voltages, and subjecting this cell to UV radiation so as to restore its threshold to the reference value. The wafer is then subjected to the plasma treatment to be assessed, and the threshold voltages of the cells are measured and compared with the reference threshold voltage so as to derive from the comparison information on the alterations induced on the dielectrics formed on the wafer and on the distribution of the plasma potential.

Abstract: The process described requires the formation of floating-gate non-volatile memory cells entirely similar in structure to those produced by known processes. The process comprises an annealing treatment at relatively low temperature (430.degree. C.) to repair damage due to plasma treatments. To obtain threshold voltage values for the cells close to the theoretical values, especially for cells with particularly extended interconnections, the cells are subjected to ultraviolet radiation before the annealing treatment, in order to neutralize any electrical charges present in the floating-gate electrodes of the cells.

Abstract: A bipolar transistor, comprising a collector region, a base region, and an emitter region, is a type which is compatible to CMOS processes leading to the formation, on a semiconductor substrate, of N-channel and P-channel MOS transistors having respective source and drain regions. In such bipolar transistor, the collector region is a substrate diffused pocket and the base region is formed within the diffused pocket simultaneously with the source and drain regions of the P-channel MOS transistors. Further, the emitter region is incorporated, in turn, to the base region simultaneously with the source and drain regions of the N-channel MOS transistors.