Abstract: Devices with increased susceptibility to ionizing radiation feature multiple parasitic transistors having leakage currents that increase with total ionizing dose (TID) due to negative threshold shifts from radiation-induced charge buildup in the field oxide. Leakage currents of parasitic edge transistors associated with active region sidewalls under a gate are enhanced using branching gate patterns that increase the number of these sidewalls. Other variations combine parasitic edge transistors with parasitic field transistors formed under the field oxide between active regions, or between n-wells and active regions. Arrays of such devices connected in parallel further multiply leakage currents, while novel compact designs increase the density and hence the sensitivity to TID for a given circuit area.

Abstract: Devices with increased susceptibility to ionizing radiation feature multiple parasitic transistors having leakage currents that increase with total ionizing dose (TID) due to negative threshold shifts from radiation-induced charge buildup in the field oxide. Leakage currents of parasitic edge transistors associated with active region sidewalls under a gate are enhanced using branching gate patterns that increase the number of these sidewalls. Other variations combine parasitic edge transistors with parasitic field transistors formed under the field oxide between active regions, or between n-wells and active regions. Arrays of such devices connected in parallel further multiply leakage currents, while novel compact designs increase the density and hence the sensitivity to TID for a given circuit area.

Abstract: Designs for radiation hardening CMOS devices and integrated circuits using shallow trench isolation (STI) improve total ionizing dose (TID) radiation response by reducing the leakage currents from source to drain associated with corners and sidewalls of trench insulator edges passing under the gate in an NMOS device while maintaining high breakdown voltage. A silicide block pattern is used in combination with pullback of N+ source and drain regions from at least a portion of these edges of the active region. Additional p-type implants along these edges further increase parasitic threshold voltages and enhance radiation hardness. A process for fabricating devices and integrated circuits incorporating these features is also provided. These techniques and processes are applied to exemplary low-voltage NMOS transistors having straight gates and to high-voltage annular-gate devices, as well as to device-to-device isolation in integrated circuits.

Abstract: Designs for radiation hardening CMOS devices and integrated circuits using shallow trench isolation (STI) improve total ionizing dose (TID) radiation response by reducing the leakage currents from source to drain associated with corners and sidewalls of trench insulator edges passing under the gate in an NMOS device while maintaining high breakdown voltage. A silicide block pattern is used in combination with pullback of N+ source and drain regions from at least a portion of these edges of the active region. Additional p-type implants along these edges further increase parasitic threshold voltages and enhance radiation hardness. A process for fabricating devices and integrated circuits incorporating these features is also provided. These techniques and processes are applied to exemplary low-voltage NMOS transistors having straight gates and to high-voltage annular-gate devices, as well as to device-to-device isolation in integrated circuits.

Abstract: Designs for radiation hardening CMOS devices and integrated circuits using shallow trench isolation (STI) improve total ionizing dose (TID) radiation response by reducing the leakage currents from source to drain associated with corners and sidewalls of trench insulator edges passing under the gate in an NMOS device while maintaining high breakdown voltage. A silicide block pattern is used in combination with pullback of N+ source and drain regions from at least a portion of these edges of the active region. Additional p-type implants along these edges further increase parasitic threshold voltages and enhance radiation hardness. A process for fabricating devices and integrated circuits incorporating these features is also provided. These techniques and processes are applied to exemplary low-voltage NMOS transistors having straight gates and to high-voltage annular-gate devices, as well as to device-to-device isolation in integrated circuits.

Abstract: Designs for radiation hardening CMOS devices and integrated circuits using shallow trench isolation (STI) improve total ionizing dose (TID) radiation response by reducing the leakage currents from source to drain associated with corners and sidewalls of trench insulator edges passing under the gate in an NMOS device while maintaining high breakdown voltage. A silicide block pattern is used in combination with pullback of N+ source and drain regions from at least a portion of these edges of the active region. Additional p-type implants along these edges further increase parasitic threshold voltages and enhance radiation hardness. A process for fabricating devices and integrated circuits incorporating these features is also provided. These techniques and processes are applied to exemplary low-voltage NMOS transistors having straight gates and to high-voltage annular-gate devices, as well as to device-to-device isolation in integrated circuits.

Abstract: A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.

Abstract: A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.

Abstract: A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.

Abstract: A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.

Abstract: A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.

Abstract: A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.

Abstract: Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a bird's beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the bird's beak region and terminating at the inner edge of the bird's beak region, a gate crossing the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the guard region. A variation of a local oxidation of silicon process is used with an additional bird's beak implantation mask as well as minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density.