Patents by Inventor Emily True

Emily True has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8299446
    Abstract: Sub-field enhanced global alignment (SEGA) methods for aligning reconstituted wafers in a lithography process are disclosed. The SEGA methods provide the ability to accommodate chip placement errors for chips supported by a reconstituted wafer when performing a lithographic process having an overlay requirement. The SEGA methods include measuring chip locations to determine sub-fields of the reconstituted wafer over which enhanced global alignment (EGA) can be performed on the chips therein to within the overlay requirement. The SEGA methods further included individually performing EGA over the respective sub-fields. The SEGA methods take advantage of the benefits of both EGA and site-by-site alignment and are particularly applicable to wafer-level packing lithographic processes such as fan-out wafer-level packaging.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: October 30, 2012
    Assignee: Ultratech, Inc.
    Inventors: Andrew M. Hawryluk, Emily True, Manish Ranjan, Warren Flack, Detlef Fuchs
  • Patent number: 8017424
    Abstract: An apparatus for measuring the relative positions of frontside and backside alignment marks located on opposite sides of a substrate is disclosed. The apparatus includes upper and lower optical systems that allow for simultaneous imaging of frontside and backside alignment marks. The frontside and backside alignment mark images are processed to determine the relative position of the marks, as a measurement of the alignment and/or overlay performance of the tool that formed the marks on the substrate.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: September 13, 2011
    Assignee: Ultratech, Inc.
    Inventors: Albert J Crespin, Jim Woodruff, Ray Ellis, Scott Kulas, Joe Jamello, Emily True
  • Publication number: 20110058731
    Abstract: An apparatus for measuring the relative positions of frontside and backside alignment marks located on opposite sides of a substrate is disclosed. The apparatus includes upper and lower optical systems that allow for simultaneous imaging of frontside and backside alignment marks. The frontside and backside alignment mark images are processed to determine the relative position of the marks, as a measurement of the alignment and/or overlay performance of the tool that formed the marks on the substrate.
    Type: Application
    Filed: November 11, 2010
    Publication date: March 10, 2011
    Applicant: Ultratech, Inc.
    Inventors: Albert J. Crespin, Jim Woodruff, Ray Ellis, Scott Kulas, Joe Jamello, Emily True
  • Patent number: 7902040
    Abstract: An apparatus for measuring the relative positions of frontside and backside alignment marks located on opposite sides of a substrate is disclosed. The apparatus includes upper and lower optical systems that allow for simultaneous imaging of frontside and backside alignment marks. The frontside and backside alignment mark images are processed to determine the relative position of the marks, as a measurement of the alignment and/or overlay performance of the tool that formed the marks on the substrate.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: March 8, 2011
    Assignee: Ultratech, Inc.
    Inventors: Albert J. Crespin, Jim Woodruff, Ray Ellis, Scott Kulas, Joe Jamello, Emily True
  • Publication number: 20110038704
    Abstract: Sub-field enhanced global alignment (SEGA) methods for aligning reconstituted wafers in a lithography process are disclosed. The SEGA methods provide the ability to accommodate chip placement errors for chips supported by a reconstituted wafer when performing a lithographic process having an overlay requirement. The SEGA methods include measuring chip locations to determine sub-fields of the reconstituted wafer over which enhanced global alignment (EGA) can be performed on the chips therein to within the overlay requirement. The SEGA methods further included individually performing EGA over the respective sub-fields. The SEGA methods take advantage of the benefits of both EGA and site-by-site alignment and are particularly applicable to wafer-level packing lithographic processes such as fan-out wafer-level packaging.
    Type: Application
    Filed: June 24, 2010
    Publication date: February 17, 2011
    Inventors: Andrew M. Hawryluk, Emily True, Ranjan Manish, Warren Flack, Detlef Fuchs
  • Patent number: 7751067
    Abstract: Methods and apparatuses are provided for positioning a substrate having a target that may be located on either the front-side or the backside of the substrate. The optical detector that views the target contains a signal-generating material that is substantially identical to the substrate material.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: July 6, 2010
    Assignee: Ultratech, Inc.
    Inventors: Emily True, Ray Ellis, Shiyu Zhang
  • Patent number: 7528937
    Abstract: An apparatus for measuring the relative positions of frontside and backside alignment marks located on opposite sides of a substrate is disclosed. The apparatus includes upper and lower optical systems that allow for simultaneous imaging of frontside and backside alignment marks. The frontside and backside alignment mark images are processed to determine the relative position of the marks, as a measurement of the alignment and/or overlay performance of the tool that formed the marks on the substrate.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: May 5, 2009
    Assignee: Ultratech, Inc.
    Inventors: Albert J. Crespin, Jim Woodruff, Ray Ellis, Scott Kulas, Joe Jamello, Emily True
  • Patent number: RE44116
    Abstract: Methods and apparatuses are provided for positioning a substrate having a target that may be located on either the front-side or the backside of the substrate. The optical detector that views the target contains a signal-generating material that is substantially identical to the substrate material.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: April 2, 2013
    Assignee: Ultratech, Inc.
    Inventors: Emily True, Ray Ellis, Shiyu Zhang