Abstract: A RU for mMIMO has M antenna branches; a plurality of partial digital beamforming (PDBF) processors, each PDBF processor receiving a transmit vector comprising values for each of L data layers to be transmitted at time t from the RU via the antenna branches, wherein each of the plurality of PDBF processors performs a beamforming operation on the vector by multiplying the vector with each of a plurality of respective weight vectors that are a subset of a received weight array, to produce scalar values, each scalar value corresponding to one of the weight vectors and being supplied to a respective antenna branch; wherein the number of scalar values produced by any particular one of the PDBF processors equals the number of weight vectors used in each PDBF processor and the number of scalar values produced is equal to M; where L and M are greater than one.

Abstract: The present invention, a Digital Power Amplifier (DPA) with filtered output relates to the transmission circuitry of wireless communications systems and more particularly to high frequency power amplifier circuits using digital intensive techniques on cost efficient semiconductor technologies. Today, we experience an ever-increasing need for low cost, low power wireless transmitters in the millimeter wavelength region. Current solutions rely on analog PA circuits. The background art does not contain a solution for bridging the gap between the operation frequencies of the digital circuits on a cost-efficient technology such as CMOS and the millimeter wavelength transmission frequencies demanded in numerous applications. The DPA allowing the direct feeding of digital data to a high frequency amplifying circuit. In this way, design challenging and costly analog processing up-conversion stages are avoided.

Abstract: The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-locked loops (HPLL) for establishing and maintaining a phase relationship between a generated output signal and a reference input signal. The DPLLs use a counter based loop to initially bring the DPLL into lock. Thereafter, the DPLLs disable the counter based loop and switch to a loop with a multi-modulus divider (MMD). The DPLLs can implement a cancellation technique to reduce phase noise introduced by the MMD. The HPLLs further include a loop with a MMD. The HPLLs can implement a similar cancellation technique to reduce phase noise introduced by the MMD.

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract: The present disclosure is directed to a fractional-N digital phase locked loop (DPLL) that replaces the conventionally used time-to-digital converter (TDC) based phase detector with a bang-bang phase detector (BBPD). Compared to the TDC based phase detector, the BBPD has an often superior resolution for the same or similar amount of power and/or area consumption. Therefore, replacing the TDC based phase detector with a BBPD can reduce, or even eliminate, the common problem of spurs being added to the output signal generated by the DPLL because of the limited resolution of the TDC based phase detector. This can allow the DPLL to be used for the most demanding applications, such as in generating local oscillator signals for down-converting and demodulating weak signals received by a communication device, such as a cellular phone.

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract: Aspects of a method and system for direct and polar modulation using a two input PLL are presented. Aspects of the system may include generating digital signals Wn and Vn from an input data signal Un and a feedback signal Yn. The generated digital signals Wn and Vn combined may carry the information content of Un while they compensate the non-idealities of the two-input analog phase locked loop (PLL). The digital signal Wn, which may be scaled appropriately in frequency, and the digital signal Vn may be provided as inputs to the PLL. The feedback signal Yn may be a digital signal that may correspond to the analog feedback signal Pt that may be generated by the PLL. Accordingly, the PLL may be adaptively controlled via the digital signals Wn and Vn for properly transmitting the input data signal Un.

Abstract: Aspects of a method and system for direct and polar modulation using a two input PLL are presented. Aspects of the system may include generating digital signals Wn and Vn from an input data signal Un and a feedback signal Yn. The generated digital signals Wn and Vn combined may carry the information content of Un while they compensate the non-idealities of the two-input analog phase locked loop (PLL). The digital signal Wn, which may be scaled appropriately in frequency, and the digital signal Vn may be provided as inputs to the PLL. The feedback signal Yn may be a digital signal that may correspond to the analog feedback signal Pt that may be generated by the PLL. Accordingly, the PLL may be adaptively controlled via the digital signals Wn and Vn for properly transmitting the input data signal Un.

Abstract: A method and system for recursively detecting MIMO signals is provided. The method may include receiving an RF vector signal comprising a plurality of transmitted subcarriers and determining an estimate of the received RF vector signal in a recursive manner on a per symbol or even a per sample basis. The method may also include normalizing a plurality of the transmitted subcarriers utilizing at least one subcarrier normalizer before performing the recursive algorithm. A systolic array may be used to process the multi-antenna received data in parallel and the state variables of the systolic array may be stored to a memory before processing the next subcarrier. The receiver and transmitter may be part of a MIMO system, where a beam-forming matrix may be communicated from the receiver to the transmitter, and the signals may conform to an OFDM standard.

Abstract: Aspects of a method and system for digital tracking in direct and polar modulation are presented. Aspects of the system may include at least one circuit within a phase locked loop (PLL) circuit that enables adaptive and digital control of an analog fractional N (Frac N) PLL during direct modulation of a signal or polar modulation of the signal.