Abstract: A variable attenuator can be used with high-voltage radio-frequency signals. The attenuator can provide wide dynamic range with little loss at the lowest attenuation level. The attenuator may be implemented in digital integrated circuit processes and occupies small integrated circuit area. Additionally, the use of circuit elements external to the SoC may be reduced. The attenuator uses multiple attenuator cells connected in parallel to an RF input and RF output. The attenuator cells use capacitive dividers with pair of capacitors laid out in the same integrated circuit area. The capacitors are also laid out so that the RF input shields the RF output from ground to avoid parasitic capacitance on the RF output.

Abstract: A variable attenuator can be used with high-voltage radio-frequency signals. The attenuator can provide wide dynamic range with little loss at the lowest attenuation level. The attenuator may be implemented in digital integrated circuit processes and occupies small integrated circuit area. Additionally, the use of circuit elements external to the SoC may be reduced. The attenuator uses multiple attenuator cells connected in parallel to an RF input and RF output. The attenuator cells use capacitive dividers with pair of capacitors laid out in the same integrated circuit area. The capacitors are also laid out so that the RF input shields the RF output from ground to avoid parasitic capacitance on the RF output.

Abstract: An oscillator circuit may selectively switch between a normal mode and a low-power mode in response to a mode signal. During the normal mode, the oscillator circuit may employ a first amplifier configuration and a first capacitive loading to generate a high-accuracy clock signal having a relatively low frequency error. During the low power mode, the oscillator circuit may employ a second amplifier configuration and a second capacitive loading to generate a low-power clock signal using minimal power consumption. A compensation circuit may be used to offset a relatively high frequency error during the low-power mode.

Abstract: A frequency synthesizer is disclosed that includes an oscillator having an output to deliver a signal of a controllable frequency. The oscillator includes a capacitor bank responsive to an N-bit control signal to exhibit a capacitance. The oscillator output frequency is based on the capacitance. Control logic generates the N-bit control signal and determines each bit of the N-bit control signal through a binary search step and a modulation of a least-significant-bit (LSB) of the N-bit control signal. The LSB modulation, combined with the binary search for each bit, results in a higher accuracy frequency estimation.

Abstract: An oscillator circuit may selectively switch between a normal mode and a low-power mode in response to a mode signal. During the normal mode, the oscillator circuit may employ a first amplifier configuration and a first capacitive loading to generate a high-accuracy clock signal having a relatively low frequency error. During the low power mode, the oscillator circuit may employ a second amplifier configuration and a second capacitive loading to generate a low-power clock signal using minimal power consumption. A compensation circuit may be used to offset a relatively high frequency error during the low-power mode.

Abstract: A frequency synthesizing system includes a clock generator to generate a reference clock signal, a frequency doubler to generate a frequency-doubled clock signal in response to rising edges and falling edges of the reference clock signal, a frequency multiplier to generate a frequency-multiplied clock signal in response to either rising edges or falling edges of the frequency-doubled clock signal, and a fractional-N synthesizer coupled to the frequency multiplier to generate an output clock signal in response to the frequency-multiplied clock signal.

Abstract: A frequency synthesizing system includes a clock generator to generate a reference clock signal, a frequency doubler to generate a frequency-doubled clock signal in response to rising edges and falling edges of the reference clock signal, a frequency multiplier to generate a frequency-multiplied clock signal in response to either rising edges or falling edges of the frequency-doubled clock signal, and a fractional-N synthesizer coupled to the frequency multiplier to generate an output clock signal in response to the frequency-multiplied clock signal.

Abstract: A frequency divider is disclosed. The frequency divider includes a multi-modulus prescaler to perform a frequency division by a modulus M, wherein M is an integer between N and 2*N?1 and N is a power of 2. The frequency divider also includes a programmable counter to output the digital representation of M and an output clock signal. For the frequency divider, M equals N plus D minus D\N for each edge of the multi-modulus prescaler output clock CKpr wherein the counter samples the digital representation of D and D\N denotes an integer part of D divided by N, and M equals N for each subsequent edge of the prescaler output clock CKpr wherein the counter does not sample the digital representation of D.

Abstract: An oscillator is disclosed that can generate an oscillation signal using a latch and two delay elements. For some embodiments, the oscillator includes an SR latch, a first delay element, and a second delay element. The SR latch has a first input, a second input, a first output, and a second output. The first delay element is coupled between the first output and the first input of the SR latch. The second delay element is coupled between the second output and the second input of the SR latch. For some embodiments, the first and second delay elements include a programmable pull-up circuit that allows the charging current to be adjusted in discrete amounts, and include a programmable capacitor circuit that allows the capacitance value to be adjusted in discrete amounts.

Abstract: A charge pump circuit is disclosed that includes a main charge pump, a replica charge pump, and an op-amp. The main charge pump includes up and down input terminals to receive UP and DN control signals, a control terminal to receive a calibration signal, and an output to generate a control voltage. The replica charge pump includes up and down input terminals to receive DN and UP control signals, a control terminal to receive the calibration signal, and an output to generate a replica voltage. The op-amp generates the calibration signal in response to the control voltage and the replica voltage.

Abstract: A clock multiplier circuit includes a clock generator, a delay element, a logic gate, and a duty cycle correction circuit. The clock generator generates a clock signal. The delay element generates a delayed clock signal in response to the clock signal. The logic gate generates a frequency-multiplied clock signal in response to the clock signal and the delayed clock signal. The duty cycle correction circuit generates an adjustment signal based at least in part on the frequency-multiplied clock signal. The clock generator adjusts a duty cycle of the clock signal in response to the adjustment signal.

Abstract: A clock generation circuit is disclosed that may generate a plurality of phase-delayed signals in a manner that may be relatively immune to VCO pulling. The clock generation circuit may include a circuit to generate an oscillating signal, a frequency divider to generate an RF signal having a frequency that is equal to 1/(n+0.5) times the frequency of the oscillating signal, wherein n is an integer value greater than or equal to one and n+0.5 is a non-integer value, and a DLL circuit to generate a plurality of local oscillator signals, wherein the local oscillator signals are phase-delayed with respect to each other.

Abstract: A charge pump circuit is disclosed that includes a main charge pump, a replica charge pump, and an op-amp. The main charge pump includes up and down input terminals to receive UP and DN control signals, a control terminal to receive a calibration signal, and an output to generate a control voltage. The replica charge pump includes up and down input terminals to receive DN and UP control signals, a control terminal to receive the calibration signal, and an output to generate a replica voltage. The op-amp generates the calibration signal in response to the control voltage and the replica voltage.

Abstract: An oscillator is disclosed that can generate an oscillation signal using a latch and two delay elements. For some embodiments, the oscillator includes an SR latch, a first delay element, and a second delay element. The SR latch has a first input, a second input, a first output, and a second output. The first delay element is coupled between the first output and the first input of the SR latch. The second delay element is coupled between the second output and the second input of the SR latch. For some embodiments, the first and second delay elements include a programmable pull-up circuit that allows the charging current to be adjusted in discrete amounts, and include a programmable capacitor circuit that allows the capacitance value to be adjusted in discrete amounts.

Abstract: A frequency divider is disclosed. The frequency divider includes a multi-modulus prescaler to perform a frequency division by a modulus M, wherein M is an integer between N and 2*N?1 and N is a power of 2. The frequency divider also includes a programmable counter to output the digital representation of M and an output clock signal. For the frequency divider, M equals N plus D minus D\N for each edge of the multi-modulus prescaler output clock CKpr wherein the counter samples the digital representation of D and D\N denotes an integer part of D divided by N, and M equals N for each subsequent edge of the prescaler output clock CKpr wherein the counter does not sample the digital representation of D.

Abstract: A frequency synthesizer is disclosed that includes an oscillator having an output to deliver a signal of a controllable frequency. The oscillator includes a capacitor bank responsive to an N-bit control signal to exhibit a capacitance. The oscillator output frequency is based on the capacitance. Control logic generates the N-bit control signal and determines each bit of the N-bit control signal through a binary search step and a modulation of a least-significant-bit (LSB) of the N-bit control signal. The LSB modulation, combined with the binary search for each bit, results in a higher accuracy frequency estimation.

Abstract: A delay-locked loop (DLL) circuit is disclosed that can generate an output oscillation signal having a frequency that is an integer multiple of an input oscillation signal. The DLL includes a phase detector, a charge pump, and a voltage-controlled oscillator (VCO). The phase detector generates UP and DN control signals in response to a phase difference between a reference signal and a feedback signal. The charge pump generates a control voltage in response to the UP and DN control signals. The VCO adjusts the frequency of the output oscillation signal in response to the control voltage, generates the reference signal in response to the input oscillation signal, and generates the feedback signal in response to the output oscillation signal.

Abstract: This disclosure involves methods and systems for suppressing undesired limit cycles in switching regulators by determining when a limit cycle causes the inductor to charge for a time greater than the clock period and destabilizing such cycles.

Abstract: This disclosure involves methods and systems for reducing the voltage by a circuit such as a switching regulator during an overvoltage event by draining current from a voltage source when voltage exceeding a desired level is generated.

Abstract: This disclosure involves systems for providing an oscillatory circuit having low phase noise featuring arrays of complementary VCO pairs connected in parallel.