Patents by Inventor Emmanuel Ardichvili

Emmanuel Ardichvili has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10997107
    Abstract: A system on chip includes an interconnect circuit including at least p input interfaces and at least k output interfaces, p source devices respectively coupled to the p input interfaces and k access ports respectively coupled to the k output interfaces and belonging to a target that includes one or more target devices. Each source device is configured to deliver transactions to the target via one of the access ports. An associated memory of each access port is configured to temporarily store the transactions received by the access port. The target is configured to deliver, for each access port, a fill signal representative of a current fill level of its associated memory. A control circuit is configured to receive the fill signals from the access ports and select the access ports eligible to receive a transaction depending on the current fill levels.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 4, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Patent number: 10983937
    Abstract: In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: April 20, 2021
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS SA
    Inventors: Olivier Ferrand, Daniel Olson, Anis Ben Said, Emmanuel Ardichvili
  • Publication number: 20200293474
    Abstract: In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.
    Type: Application
    Filed: February 26, 2020
    Publication date: September 17, 2020
    Inventors: Olivier Ferrand, Daniel Olson, Anis Ben Said, Emmanuel Ardichvili
  • Patent number: 10740141
    Abstract: A system on chip includes an interconnect circuit having an input interface and a number of output interfaces. A source device is coupled to the input interface. A target device includes a sectorized addressable memory space and a number of access ports respectively coupled to the output interfaces. The source device is configured to deliver a transaction containing an address word to the target device.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: August 11, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Patent number: 10698843
    Abstract: An interconnect circuit includes a plurality of input interfaces and a plurality of output interfaces. A plurality of source devices are respectively coupled to the input interfaces. A target device has a plurality of access ports respectively coupled to the output interfaces. Each source device is configured to deliver transactions to the target device. Programmable control circuit is configured to deliver, to the interconnect circuit, a control word designating an access port assigned to this source device. The interconnect circuit is configured to route the transaction from the corresponding input interface to the output interface that is coupled to this access port and to deliver the transaction to the access port, the content of each transaction delivered to an access port being identical to the content of the corresponding transaction delivered by the source equipment whatever the selected access port.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: June 30, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Publication number: 20200174964
    Abstract: A system includes a plurality of items of master equipment, each having a programing interface, and a plurality of slave equipment. An interconnect circuit is coupled between the items of master equipment and the items of slave equipment. Each transaction is assigned an attribute capable of taking on at least two attribute values corresponding to at least two states for the master equipment. Each item of slave equipment is associated with an identifier capable of taking on at least two values corresponding respectively to at least two properties for the slave equipment. Each item of master equipment automatically inherits the property of its programing interface. A filtering circuit is configured to, in the presence of a transaction intended for an item of slave equipment, compare the corresponding attribute value with an identifier value of the intended slave equipment and reject or not reject the transaction based on the comparison.
    Type: Application
    Filed: November 14, 2019
    Publication date: June 4, 2020
    Inventors: Emmanuel Ardichvili, Laurent Lestringand, Patrick Valdenaire
  • Publication number: 20200026679
    Abstract: A system on chip includes an interconnect circuit including at least p input interfaces and at least k output interfaces, p source devices respectively coupled to the p input interfaces and k access ports respectively coupled to the k output interfaces and belonging to a target that includes one or more target devices. Each source device is configured to deliver transactions to the target via one of the access ports. An associated memory of each access port is configured to temporarily store the transactions received by the access port. The target is configured to deliver, for each access port, a fill signal representative of a current fill level of its associated memory. A control circuit is configured to receive the fill signals from the access ports and select the access ports eligible to receive a transaction depending on the current fill levels.
    Type: Application
    Filed: July 8, 2019
    Publication date: January 23, 2020
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Publication number: 20190317799
    Abstract: A system on chip includes an interconnect circuit having an input interface and a number of output interfaces. A source device is coupled to the input interface. A target device includes a sectorized addressable memory space and a number of access ports respectively coupled to the output interfaces. The source device is configured to deliver a transaction containing an address word to the target device.
    Type: Application
    Filed: March 22, 2019
    Publication date: October 17, 2019
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Publication number: 20190266108
    Abstract: An interconnect circuit includes a plurality of input interfaces and a plurality of output interfaces. A plurality of source devices are respectively coupled to the input interfaces. A target device has a plurality of access ports respectively coupled to the output interfaces. Each source device is configured to deliver transactions to the target device. Programmable control circuit is configured to deliver, to the interconnect circuit, a control word designating an access port assigned to this source device. The interconnect circuit is configured to route the transaction from the corresponding input interface to the output interface that is coupled to this access port and to deliver the transaction to the access port, the content of each transaction delivered to an access port being identical to the content of the corresponding transaction delivered by the source equipment whatever the selected access port.
    Type: Application
    Filed: February 13, 2019
    Publication date: August 29, 2019
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Patent number: 8312355
    Abstract: An integrated circuit configurable to encode data according to a number of coding schemes and to generate cyclic redundancy codes, includes a number of identical specific hardware cells, and each cell includes four outputs for binary signals, four inputs for binary signals, a buffer to delay by one clock period a binary value received on an input and to output a one-clock period delayed binary value, binary adders to perform XOR operations, configurable multiplexers connecting the outputs, the inputs, the buffer and the adders to each other according to several configurable paths, and controllable switch matrices external to each cell and able to electrically connect and disconnect inputs to or from outputs of another cell.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: November 13, 2012
    Assignee: ST-Ericsson SA
    Inventors: Martial Gander, Emmanuel Ardichvili
  • Publication number: 20100115378
    Abstract: An integrated circuit configurable to encode data according to a number of coding schemes and to generate cyclic redundancy codes, includes a number of identical specific hardware cells, and each cell includes four outputs for binary signals, four inputs for binary signals, a buffer to delay by one clock period a binary value received on an input and to output a one-clock period delayed binary value, binary adders to perform XOR operations, configurable multiplexers connecting the outputs, the inputs, the buffer and the adders to each other according to several configurable paths, and controllable switch matrices external to each cell and able to electrically connect and disconnect inputs to or from outputs of another cell.
    Type: Application
    Filed: November 12, 2007
    Publication date: May 6, 2010
    Inventors: Martial Gander, Emmanuel Ardichvili
  • Patent number: 7710942
    Abstract: The present invention relates to a method of performing time drift compensation in a receiver (200) and a receiver (200) for performing time drift compensation. The basic idea of the invention is that a signal is received at the receiver. A control pulse is produced after a certain number of chips of the received signal has been received. A variable delay that is applied to the received signal is controlled by means of the control pulse. The resulting delayed signal is supplied to demodulation units (202, 203) in the receiver, in which delayed signal chips have been omitted or duplicated. A compensation signal is supplied to the demodulation units in the receiver, and this compensation signal indicates whether chips have been omitted or duplicated in the delayed signal. Finally, the delayed signal is demodulated such that the demodulation units consider the omission or duplication of chips in the delayed signal.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: May 4, 2010
    Assignee: ST-Ericsson SA
    Inventors: Emmanuel Ardichvili, Martial Gander
  • Publication number: 20070160119
    Abstract: The present invention relates to a method of performing time drift compensation in a receiver (200) and a receiver (200) for performing time drift compensation. The basic idea of the invention is that a signal is received at the receiver. A control pulse is produced after a certain number of chips of the received signal has been received. A variable delay that is applied to the received signal is controlled by means of the control pulse. The resulting delayed signal is supplied to demodulation units (202, 203) in the receiver, in which delayed signal chips have been omitted or duplicated. A compensation signal is supplied to the demodulation units in the receiver, and this compensation signal indicates whether chips have been omitted or duplicated in the delayed signal. Finally, the delayed signal is demodulated such that the demodulation units consider the omission or duplication of chips in the delayed signal.
    Type: Application
    Filed: December 14, 2004
    Publication date: July 12, 2007
    Applicant: Koninklijke Philips Electronics N.V.
    Inventors: Emmanuel Ardichvili, Martial Gander
  • Publication number: 20060056542
    Abstract: The present invention relates to a delay line (D LINE) for delaying an input sig al, said input signal comprising a series of samples (IN TIME, LATE, VOID). The nvention is characterized in that it is intended to delay the input signal by a eries of delays and that the series is divided into a series of delay sub-lines ZONE) each intended to write one sample from the series of samples (IN TIME, EAR Y, LATE, VOID) of said input signal, and in that it comprises control means (RD DD GEN) intended to generate read addresses of the samples in the delay sub-line (ZONE) from the series of samples (IN TIME, EARLY, LATE, VOID) of the input sig al. The read addresses are equal to a difference between a write address of a sa ple in the delay sub-lines (ZONE) of the input signal and said delays expressed n a number of chip periods.
    Type: Application
    Filed: August 5, 2003
    Publication date: March 16, 2006
    Inventors: Emmanuel Ardichvili, Christophe Floret