Abstract: A critical data path of an integrated circuit includes a flip flop configured to receive a data input and provide a latched data output. A monitoring circuit includes a delay generator configured to receive the data input and provide a plurality of delayed data outputs corresponding to delayed versions of the data input with increasing amounts of delay, a selector circuit configured to select one of the plurality of delayed outputs based on a programmable control value, and a shadow latch coupled to an output of the selector circuit and configured to latch a value at its input to provide as a latched shadow output. A comparator circuit provides a match error indicator based on a comparison between the first latched data output and the latched shadow output, and an error indicator is provided which indicates whether or not an impending failure of the critical data path is detected.

Abstract: A method and apparatus for reducing dynamic switching current in high speed logic. The apparatus may include a CMOS logic circuit, which in turn includes an NMOS FinFET, a first PMOS FinFET, and a second PMOS FinFET. A gate of the NMOS FinFET is connected to a gate of the first PMOS FinFET, a drain of the NMOS FinFET is connected to a drain of the first PMOS FinFET, and the second PMOS FinFET is connected to the first PMOS FinFET to create a capacitor between a source and the drain of the first PMOS FinFET. In one embodiment, the second PMOS FinFET is contained in and positioned at an edge of a cell that also contains the first PMOS FinFET and the NMOS FinFET.

Abstract: An LVT-RVT cell includes an LVT PMOS transistor adjacent to an RVT NMOS transistor, whereby the LVT and RVT transistors are placed inside a common p-well and are biased using the same voltage potential. The cell thus employs a flipped well for the PMOS transistor and a conventional (unflipped) well for the NMOS transistor. By arranging the LVT-RVT cell in this way, the cell can function at lower voltages, thereby conserving power, while also improving the performance of the composite function. Furthermore, the LVT-RVT cell can be placed adjacent to RVT cells to further reduce power consumption and improve performance of the RVT cells within the block.

Abstract: A method and apparatus for reducing dynamic switching current in high speed logic. The apparatus may include a CMOS logic circuit, which in turn includes an NMOS FinFET, a first PMOS FinFET, and a second PMOS FinFET. A gate of the NMOS FinFET is connected to a gate of the first PMOS FinFET, a drain of the NMOS FinFET is connected to a drain of the first PMOS FinFET, and the second PMOS FinFET is connected to the first PMOS FinFET to create a capacitor between a source and the drain of the first PMOS FinFET. In one embodiment, the second PMOS FinFET is contained in and positioned at an edge of a cell that also contains the first PMOS FinFET and the NMOS FinFET.