Patents by Inventor Emmanuel Espiritu

Emmanuel Espiritu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9659897
    Abstract: A system and a method of manufacture thereof of integrated circuit packaging system, including: a pillar; a conductive buildup attached to the pillar; and a molded body encapsulating the conductive buildup, the pillar extending out of the molded body.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 23, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Bartholomew Liao Chung Foh, Dao Nguyen Phu Cuong, Jeffrey David Punzalan
  • Patent number: 9355983
    Abstract: A system and a method of manufacture thereof of integrated circuit packaging system, including: a pillar; a conductive buildup attached to the pillar; and a molded body encapsulating the conductive buildup, the pillar extending out of the molded body.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: May 31, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Bartholomew Liao Chung Foh, Dao Nguyen Phu Cuong, Jeffrey David Punzalan
  • Patent number: 9305809
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: discrete components coupled to a top trace; vias attached to the top trace separated from the discrete components; a dielectric layer on the top trace, the discrete components, and the vias, includes a component surface formed above the discrete components, with the top trace coplanar with the dielectric layer; and system interconnects coupled to the vias for electrically connecting the top trace, the discrete components, or a combination thereof to the system interconnects.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: April 5, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Emmanuel Espiritu, Allan Pumatong Ilagan, Jeffrey David Punzalan
  • Patent number: 9293351
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: March 22, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua, Emmanuel Espiritu
  • Patent number: 9281300
    Abstract: A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the BGA substrate, and an application die attached to the IPD. A method of manufacturing a semiconductor package includes providing a BGA substrate having integrated metal layer circuitry, attaching a flip chip CSMP having a first IPD to the BGA substrate, and attaching an application die to the IPD.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: March 8, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Leo A. Merilo, Emmanuel A. Espiritu, Dario S. Filoteo, Jr., Rachel L. Abinan
  • Patent number: 9076737
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base strip having a base top side; forming a terminal body with a substantially spherical shape partially in the base strip; attaching a device adjacent the terminal body and over the base top side, a device mount side of the device below a top portion of the terminal body; attaching a device connector to the device and the top portion of the terminal body; applying an encapsulant over the device connector, the device, and the top portion of the terminal body; and removing the base strip providing the terminal body partially exposed from the encapsulant.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: July 7, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Jose Alvin Caparas, Lionel Chien Hui Tay
  • Patent number: 9059151
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having an upper structure, upper protrusions, and a base side facing away from the upper structure and the upper protrusions; forming tie bars in the leadframe with an opening surrounding the upper structure, the tie bars connected to the upper structure and exposed on the base side; connecting an integrated circuit to the upper protrusions; applying an encapsulant over the integrated circuit, over the upper structure, and in the opening with the base side exposed; removing the tie bars exposing a first surface and a second surface of the encapsulant below the first surface, and forming a die paddle from the upper structure and exposed from the second surface; and removing the leadframe from the base side forming island terminals from the upper protrusions exposed from the second surface and isolated from the die paddle.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: June 16, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Patent number: 9048228
    Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a leadframe having a side solderable lead with a half-etched lead portion and a lead top side; a mold body directly on the leadframe and the side solderable lead, the lead top side of the side solderable lead exposed from the mold body; a mold groove in the mold body and in a portion of the side solderable lead for exposing a lead protrusion of the side solderable lead on an upper perimeter side of the mold body; and the half-etched lead portion exposed from a lower perimeter side of the mold body.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: June 2, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Emmanuel Espiritu, Allan P. Ilagan, Marites Laguipo Roque
  • Patent number: 9035440
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent to the package paddle; depositing a lead conductive cap on the lead, the lead conductive cap includes a nickel layer having a thickness between 2.55 ?m to 8.00 ?m deposited on the lead, a palladium layer deposited on the nickel layer, and a gold layer deposited on the palladium layer; mounting an integrated circuit over the package paddle; attaching an electrical connector between the lead conductive cap and the integrated circuit; and forming an encapsulation over the integrated circuit, a portion of the lead, and a portion of the package paddle.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: May 19, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Emmanuel Espiritu, Elizar Andres, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Patent number: 9006031
    Abstract: A semiconductor device has a carrier with a die attach area. Recesses are formed partially through the carrier outside the die attach area. A first conductive layer is conformally applied over a surface of the carrier and into the recesses. A semiconductor die is mounted to the die attach area of the carrier. An encapsulant is deposited over the carrier and semiconductor die. The encapsulant extends into the recesses over the first conductive layer to form encapsulant bumps. The carrier is removed to expose the first conductive layer over the encapsulant bumps. A first insulating layer is formed over the semiconductor die with openings to expose contact pads of the semiconductor die. A second conductive layer is formed between the first conductive layer and the contact pads on the semiconductor die. A second insulating layer is formed over the second conductive layer and semiconductor die.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: April 14, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Henry D. Bathan, Emmanuel A. Espiritu
  • Patent number: 9000579
    Abstract: An integrated circuit package system includes a substrate having an opening provided therein, forming a conductor in the opening having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: April 7, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Il Kwon Shim, Dario S. Filoteo, Jr., Emmanuel Espiritu, Rachel Layda Abinan
  • Patent number: 8993376
    Abstract: A semiconductor device has a base substrate with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base substrate. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base substrate and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base substrate. A portion of the second surface of the base substrate is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Emmanuel A. Espiritu, Henry D. Bathan, Dioscoro A. Merilo
  • Publication number: 20150084172
    Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a leadframe having a side solderable lead with a half-etched lead portion and a lead top side; a mold body directly on the leadframe and the side solderable lead, the lead top side of the side solderable lead exposed from the mold body; a mold groove in the mold body and in a portion of the side solderable lead for exposing a lead protrusion of the side solderable lead on an upper perimeter side of the mold body; and the half-etched lead portion exposed from a lower perimeter side of the mold body.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Inventors: Byung Tai Do, Emmanuel Espiritu, Allan P. Ilagan, Marites Laguipo Roque
  • Patent number: 8936971
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle group having a first package paddle electrically isolated from a second package paddle; attaching an integrated circuit device on the first package paddle and the second package paddle; forming a standoff terminal adjacent the package paddle group and electrically connected to the integrated circuit device; connecting a paddle connector to the integrated circuit device and the first package paddle and another paddle connector to the integrated circuit device and the second package paddle; and forming an encapsulation over the integrated circuit device, the first package paddle, the second package paddle, and the standoff terminal, the encapsulation exposing a portion of the first package paddle, the second package paddle, and the standoff terminal.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: January 20, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Patent number: 8912046
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming signal contacts; forming a power bar having a power bar terminal, the power bar terminal formed in a staggered position relative to the signal contacts; depositing a terminal pad on the power bar terminal; depositing a contact pad on one of the signal contacts; coupling an integrated circuit die to the power bar terminal and the signal contacts; and forming a package body on the integrated circuit die.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: December 16, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Emmanuel Espiritu, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Patent number: 8866275
    Abstract: A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: October 21, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Dioscoro A. Merilo, Henry D. Bathan, Emmanuel A. Espiritu
  • Patent number: 8809119
    Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a leadframe having unprocessed leads; depositing an etch mask on a top surface of the unprocessed leads, the unprocessed leads having the etch mask and an unmasked portions of the top surface; connecting an integrated circuit die to the unprocessed leads; encapsulating with a package body the leadframe, the top surface of the unprocessed leads exposed from the package body; forming side-solderable leads including forming a groove in the unprocessed leads, the groove formed under a portion of the etch mask including forming an overhang of the etch mask over the groove; removing the etch mask; and depositing a plating on the side-solderable leads.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: August 19, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Emmanuel Espiritu, Henry Descalzo Bathan, Byung Tai Do
  • Patent number: 8802501
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having an upper hole below a paddle top side, the upper hole bounded by an upper non-horizontal side with a curve surface; forming a terminal adjacent the package paddle; mounting an integrated circuit on the paddle top side; and forming an encapsulation within the upper hole.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: August 12, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu, Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8803300
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead-frame having a die attach paddle and a contact pad connected by a link; mounting an integrated circuit die over the die attach paddle; molding a package body on the lead-frame and the integrated circuit die including leaving portions of the die attach paddle, the contact pad, and the link exposed from the package body; forming an exposed edge by etching away the link between the contact pad, and the die attach paddle; and depositing a solder-resistant layer on the exposed edge.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: August 12, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Emmanuel Espiritu, Jeffrey D. Punzalan
  • Patent number: 8723324
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead bottom side and a lead top side; applying a passivation over the lead with the lead top side exposed from the passivation; forming an interconnect structure directly on the passivation and the lead top side, the interconnect structure having an inner pad and an outer pad with a recess above the lead top side; mounting an integrated circuit over the inner pad and the passivation; and molding an encapsulation over the integrated circuit.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: May 13, 2014
    Assignee: Stats ChipPac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu, Dioscoro A. Merilo