Abstract: The method includes, at a first clock cycle:—obtaining (202) new requests by the processing stage;—supplying (210) by the processing stage at least one of the new requests;—placing on standby (212) by the processing stage at least one further new request, hereinafter referred to as a standby request. The method further includes, at a second clock cycle following the first clock cycle:—obtaining (202) at least one new request by the processing stage;—selecting (208) by the processing stage, from the standby request(s) and the new request(s), at least one request;—la supplying (210) the selected request(s) by the processing stage.

Abstract: The method includes:—pre-compiling a source code including determining (212), in the source code, the presence of one or a plurality of array computations on one or a plurality of arrays, referred to as input arrays, the result whereof is assigned to an array, referred to as a result array, and modifying (214) the source code according to the array computation(s) for which the presence has been determined; and—compiling (238) the modified source in machine code intended to be executed by a computer system, referred to as a target computer system, having a processor, the compiling (238) of the modified source code including compiling the command instructions in instructions which, when executed by the processor of the target computer system, command a specialized electronic device, different from the processor, to carry out each array computation detected.

Abstract: The method includes: —pre-compiling a source code including determining (212), in the source code, the presence of one or a plurality of array computations on one or a plurality of arrays, referred to as input arrays, the result whereof is assigned to an array, referred to as a result array, and modifying (214) the source code according to the array computation(s) for which the presence has been determined; and —compiling (238) the modified source in machine code intended to be executed by a computer system, referred to as a target computer system, having a processor, the compiling (238) of the modified source code including compiling the command instructions in instructions which, when executed by the processor of the target computer system, command a specialised electronic device, different from the processor, to carry out each array computation detected.

Abstract: The method includes, at a first clock cycle: obtaining (202) new requests by the processing stage; supplying (210) by the processing stage at least one of the new requests;—placing on standby (212) by the processing stage at least one further new request, hereinafter referred to as a standby request. The method further includes, at a second clock cycle following the first clock cycle:—obtaining (202) at least one new request by the processing stage;—selecting (208) by the processing stage, from the standby request(s) and the new request(s), at least one request;—la supplying (210) the selected request(s) by the processing stage.

Abstract: The packet interleaving method includes selecting successive input sets of consecutive input packets (X1 . . . XNin) received from a forward correction module (14), each input packet (Xj) being a vector of constellation points of a predetermined constellation diagram. For each input set, it further includes generating an output set of output packets (O1 . . . ONout), each output packet (Om) being a vector of constellation points, by distributing the constellation points of each input packet (Xj) of the input set, and sending the output packets (O1 . . . ONout) of the output set to a modulator (18). The input set including Nin input packets (X1 . . . XNin) and each of the Nin input packets (X1 . . . XNin) including a same number Lin of constellation points, the number Nout of output packets in the output set is related to Lin by the relation Lin=A×Nout, where A is a fixed whole number.

Abstract: The packet interleaving method includes selecting successive input sets of consecutive input packets (X1 . . . XNin) received from a forward correction module (14), each input packet (Xj) being a vector of constellation points of a predetermined constellation diagram. For each input set, it further includes generating an output set of output packets (O1 . . . ONout), each output packet (Om) being a vector of constellation points, by distributing the constellation points of each input packet (Xj) of the input set, and sending the output packets (O1 . . . ONout) of the output set to a modulator (18). The input set including Nin input packets (X1 . . . XNin) and each of the Nin input packets (X1 . . . XNin) including a same number Lin of constellation points, the number Nout of output packets in the output set is related to Lin by the relation Lin=A×Nout, where A is a fixed whole number.

Abstract: A reception device includes a number of reception paths and a decoder. The reception paths are sequenced and each reception path includes a calculation module embodied to deliver a combined confidence index and a combined data stream, from the confidence index and the equalized data stream for the current path, as well as, for the subsequent reception paths after the first path, from the combined confidence index and the combined data stream, for the preceding path. The decoder is embodied to only process the combined confidence index and the combined data stream, provided by the calculation module in the last path.

Abstract: A method of detecting an impulse noise component for a data transmission signal in a mobile environment includes receiving over a communication channel a demodulated signal having an input signal level subject to a fading condition where the input signal level varies without the presence of the impulse noise component; estimating a variation of the input signal level independently of the impulse noise component under the fading condition to obtain a robust signal level estimate of the signal; and detecting the impulse noise component based on the robust signal level estimate and the input signal level. The method also includes reducing the impulse noise component by cancelling a signal component of the received signal whose impulse noise component has been detected.

Abstract: A wireless signal amplification system including amplification apparatus (6) consisting of numerous different amplifiers (61 to 6n) which are distributed in an analogue processing chain (4). Also, a converter (12) for converting analogue signals into digital signals which, at input, are connected to the outlet of the analogue processing chain (4) and, at output, are connected to at least the gain control circuit (16) of the amplification apparatus (6) according to a value that is representative of a characteristic of the wireless signal (1). In this way, sampling of the wireless signal (1) by the converter (12) is optimized. The gain control circuit (16) establishes an average gain control signal (18), and also has, for each of the amplifiers (61 to 6n), a device for calculating an individual gain control signal (20i to 20n) according to a transfer function (H1 to Hn) which is specific to each amplifier and which is applied to the average gain control signal.

Abstract: The invention relates to a reception device comprising a number of reception paths (1 to N) and a decoder (30) with weighted inputs. Each reception path (1to N) receives an input of a data stream, corresponding to a modulated signal and embodied to provide a confidence index (CSIi) and an equalized data stream (Zi) from the received data stream. Said device is characterised in that the reception paths (1 to N) comprises a calculation module (24i) embodied to deliver a combined confidence index (CCSIi) and a combined data stream (CZi), from said confidence index (CSIi) and said equalised data stream (CZi) for the preceding path. The decoder (30) with weighted inputs is embodied to only process the combined confidence index (CCSIi) and the combined data stream (CZi), provided by the calculation module (24N) in the last path (N). The above particularly finds application in the reception of multi-channel signals for hertzian digital television.

Abstract: The invention concerns a method for synchronization upon reception of a received signal obtained by adding a plurality of transmission signals, all corresponding to the same source signal comprising data blocks called symbols of predetermined duration. The invention is characterized in that it comprises: a step which consists in determining a signal representing inferences between the symbols called intersymbol inferences; a step which consists in determining times of minimum interference level which correspond to markers of the beginning of symbols and of said symbol duration, of the reception of said received signal. The invention is in particular applicable to terrestrial digital television.

Abstract: A wireless signal amplification system including amplification apparatus (6) consisting of numerous different amplifiers (61 to 6n) which are distributed in an analogue processing chain (4). Also, a converter (12) for converting analogue signals into digital signals which, at input, are connected to the outlet of the analogue processing chain (4) and, at output, are connected to at least the gain control circuit (16) of the amplification apparatus (6) according to a value that is representative of a characteristic of the wireless signal (1). In this way, sampling of the wireless signal (1) by the converter (12) is optimized. The gain control circuit (16) establishes an average gain control signal (18), and also has, for each of the amplifiers (61 to 6n), a device for calculating an individual gain control signal (20i to 20n) according to a transfer function (H1 to Hn) which is specific to each amplifier and which is applied to the average gain control signal.

Abstract: A timing recovery circuit in a QAM demodulator which uses a symbol rate continuously adaptive interpolation filter. The method of interpolation used in the present invention is defined as a function of time per interpolation interval, rather than as a function of time per sampling interval as is commonly implemented in the prior art. This allows the interpolation filtering to be totally independent of the symbol rate in terms of complexity and performance and provides a better rejection of adjacent channels, since the interpolator rejects most of the signal outside the bandwidth of the received channel.

Abstract: A quadrature amplitude modulation type demodulator having a dual bit error rate estimator unit that allows for high bit error rate measurements. The dual bit error rate estimator circuit uses information pertaining to the number of corrected bytes from a forward error correction decoder and the count of recognizable patterns of the frame over a sufficiently large number of frames. The two pieces of information can be compared at the bit error rate levels, where both the pattern recognition counter and the FEC decoder are able to output valid data. A comparison between the two pieces of information provides a way to detect the type of noise which occurs on the network and makes it easier to correct problems in signal transmission.

Abstract: A QAM demodulator having a carrier recovery circuit that includes a phase estimation circuit and an additive noise estimation circuit which produces an estimation of the residual phase noise and additive noise viewed by the QAM demodulator. The phase noise estimation is based on the least mean square error between the QAM symbol decided by a symbol decision circuit and the received QAM symbol. The additive noise estimation is based on the same error as in the phase noise estimation, except that it is based only on QAM symbols having the minimum amplitude on the I and Q coordinates. The additive noise estimation is not dependent on the phase of the signal, thus, is independent of the phase noise estimator.

Abstract: A quadrature amplitude modulation (QAM) type demodulator having a pair of direct digital synthesizer (DDS) circuits. The first DDS circuit is located in a baseband conversion circuit before a receive filter and digitally tunes the signal within the receive filter bandwidth. The second DDS circuit is within a carrier recovery circuit located after the receive filter and serves to fine tune the signal phase.

Abstract: A QAM demodulator having a first automatic gain control circuit which outputs a first signal that is a function of the received signal, the first signal being used to control the gain of an amplifier which supplies the input of an A/D converter, and a second automatic gain controller which outputs a second signal derived from the QAM circuit after filtering, the second signal controlling the gain of a digital multiplier which produces a signal which feeds into a equalizer by way of a receive filter. The dual automatic gain control circuits, situated before and after the receive filters, allow for better resistance to non-linearity caused by signals in adjacent channels. Additionally, the dual automatic gain control circuits allow for the amplification level of the signal to be limited before the demodulator to eliminate signal distortion and to be set to the correct level internally with digital gain. Also, there is no saturation of the A/D converter since there is no QAM feedback to analog circuits.