Patents by Inventor Emmanuel Petitprez
Emmanuel Petitprez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11818901Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.Type: GrantFiled: September 29, 2021Date of Patent: November 14, 2023Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SASInventors: Philippe Boivin, Jean Jacques Fagot, Emmanuel Petitprez, Emeline Souchier, Olivier Weber
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Publication number: 20230307486Abstract: A method for manufacturing an optoelectronic device includes providing a support supporting a plurality of three-dimensional semiconductor structures, forming a sacrificial portion under a first set of 3D structures of the plurality of three-dimensional semiconductor structures, forming a barrier portion around the sacrificial portion, said barrier portion having a basal wall extending under the sacrificial portion, and a lateral wall extending at the edge of the sacrificial portion, forming an access trench up to the sacrificial portion, the access trench extending continuously along the lateral wall of the barrier portion, etching the sacrificial portion from the access trench, and removing the first set of 3D structures.Type: ApplicationFiled: August 10, 2021Publication date: September 28, 2023Inventors: Xavier HUGON, Eric POURQUIER, Frédéric MAYER, Thomas LACAVE, Philippe GIBERT, Mickae?l REBAUD, Emmanuel PETITPREZ
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Publication number: 20220020816Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.Type: ApplicationFiled: September 29, 2021Publication date: January 20, 2022Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SASInventors: Philippe BOIVIN, Jean Jacques FAGOT, Emmanuel PETITPREZ, Emeline SOUCHIER, Olivier WEBER
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Patent number: 11152430Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.Type: GrantFiled: April 4, 2019Date of Patent: October 19, 2021Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SASInventors: Philippe Boivin, Jean Jacques Fagot, Emmanuel Petitprez, Emeline Souchier, Olivier Weber
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Publication number: 20190312088Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.Type: ApplicationFiled: April 4, 2019Publication date: October 10, 2019Inventors: Philippe BOIVIN, Jean Jacques FAGOT, Emmanuel PETITPREZ, Emeline SOUCHIER, Olivier WEBER
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Patent number: 9922871Abstract: An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provided and an electrically conductive contact extends within the insulating multilayer to emerge onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.Type: GrantFiled: January 9, 2017Date of Patent: March 20, 2018Assignee: STMicroelectronics (Crolles 2) SASInventor: Emmanuel Petitprez
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Publication number: 20170117178Abstract: An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provided and an electrically conductive contact extends within the insulating multilayer to emerge onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.Type: ApplicationFiled: January 9, 2017Publication date: April 27, 2017Applicant: STMicroelectronics (Crolles 2) SASInventor: Emmanuel Petitprez
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Patent number: 9608080Abstract: An aspect of the invention is directed to a silicon-on-insulator device including a silicon layer on an insulating layer on a substrate; a raised source and a raised drain on the silicon layer; a gate between the raised source and the raised drain; a first spacer separating the gate from the raised source and substantially covering a first sidewall of the gate; a second spacer separating the gate from the raised drain and substantially covering a second sidewall of the gate; and a low-k layer over the raised source, the raised drain, the gate and each of the first spacer and the second spacer; and a dielectric layer over the low-k layer.Type: GrantFiled: March 5, 2015Date of Patent: March 28, 2017Assignees: International Business Machines Corporation, STMICROELECTRONICS (CROLLES 2) SASInventors: Ahmet S. Ozcan, Emmanuel Petitprez
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Patent number: 9590064Abstract: An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provided and an electrically conductive contact extends within the insulating multilayer to emerging onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.Type: GrantFiled: December 8, 2015Date of Patent: March 7, 2017Assignee: STMicroelectronics (Crolles 2) SASInventor: Emmanuel Petitprez
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Publication number: 20160372562Abstract: An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provide and an electrically conductive contact extends within the insulating multilayer to emerging onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.Type: ApplicationFiled: December 8, 2015Publication date: December 22, 2016Applicant: STMicroelectronics (Crolles 2) SASInventor: Emmanuel Petitprez
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Publication number: 20160260811Abstract: An aspect of the invention is directed to a silicon-on-insulator device including a silicon layer on an insulating layer on a substrate; a raised source and a raised drain on the silicon layer; a gate between the raised source and the raised drain; a first spacer separating the gate from the raised source and substantially covering a first sidewall of the gate; a second spacer separating the gate from the raised drain and substantially covering a second sidewall of the gate; and a low-k layer over the raised source, the raised drain, the gate and each of the first spacer and the second spacer; and a dielectric layer over the low-k layer.Type: ApplicationFiled: March 5, 2015Publication date: September 8, 2016Inventors: Ahmet S. Ozcan, Emmanuel Petitprez
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Patent number: 8848417Abstract: A structure for storing a native binary code in an integrated circuit, including an array of planar MIM capacitors above an insulating layer formed above a copper metallization network, wherein at least one metallization portion is present under each MIM capacitor. The size of the portion(s) is selected so that from 25 to 75% of the MIM capacitors have a breakdown voltage smaller by at least 10% than that of the other MIM capacitors.Type: GrantFiled: September 7, 2012Date of Patent: September 30, 2014Assignee: STMicroelectronics (Crolles 2) SASInventor: Emmanuel Petitprez
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Publication number: 20130083586Abstract: A structure for storing a native binary code in an integrated circuit, including an array of planar MIM capacitors above an insulating layer formed above a copper metallization network, wherein at least one metallization portion is present under each MIM capacitor. The size of the portion(s) is selected so that from 25 to 75% of the MIM capacitors have a breakdown voltage smaller by at least 10% than that of the other MIM capacitors.Type: ApplicationFiled: September 7, 2012Publication date: April 4, 2013Applicant: STMICROELECTRONICS (CROLLES 2) SASInventor: Emmanuel Petitprez
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Patent number: 8202798Abstract: An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterized in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.Type: GrantFiled: September 20, 2007Date of Patent: June 19, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Greg Braeckelmann, Hisao Kawasaki, Marius Orlowski, Emmanuel Petitprez
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Publication number: 20100314769Abstract: An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterised in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.Type: ApplicationFiled: September 20, 2007Publication date: December 16, 2010Applicant: Freescale Semiconductor, Inc.Inventors: Greg Braeckelmann, Hisao Kawasaki, Marius Orlowski, Emmanuel Petitprez