Patents by Inventor Emmanuel Petitprez

Emmanuel Petitprez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220020816
    Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.
    Type: Application
    Filed: September 29, 2021
    Publication date: January 20, 2022
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe BOIVIN, Jean Jacques FAGOT, Emmanuel PETITPREZ, Emeline SOUCHIER, Olivier WEBER
  • Patent number: 11152430
    Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: October 19, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Boivin, Jean Jacques Fagot, Emmanuel Petitprez, Emeline Souchier, Olivier Weber
  • Publication number: 20190312088
    Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.
    Type: Application
    Filed: April 4, 2019
    Publication date: October 10, 2019
    Inventors: Philippe BOIVIN, Jean Jacques FAGOT, Emmanuel PETITPREZ, Emeline SOUCHIER, Olivier WEBER
  • Patent number: 9922871
    Abstract: An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provided and an electrically conductive contact extends within the insulating multilayer to emerge onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: March 20, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Emmanuel Petitprez
  • Publication number: 20170117178
    Abstract: An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provided and an electrically conductive contact extends within the insulating multilayer to emerge onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.
    Type: Application
    Filed: January 9, 2017
    Publication date: April 27, 2017
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Emmanuel Petitprez
  • Patent number: 9608080
    Abstract: An aspect of the invention is directed to a silicon-on-insulator device including a silicon layer on an insulating layer on a substrate; a raised source and a raised drain on the silicon layer; a gate between the raised source and the raised drain; a first spacer separating the gate from the raised source and substantially covering a first sidewall of the gate; a second spacer separating the gate from the raised drain and substantially covering a second sidewall of the gate; and a low-k layer over the raised source, the raised drain, the gate and each of the first spacer and the second spacer; and a dielectric layer over the low-k layer.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: March 28, 2017
    Assignees: International Business Machines Corporation, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Ahmet S. Ozcan, Emmanuel Petitprez
  • Patent number: 9590064
    Abstract: An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provided and an electrically conductive contact extends within the insulating multilayer to emerging onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: March 7, 2017
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Emmanuel Petitprez
  • Publication number: 20160372562
    Abstract: An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provide and an electrically conductive contact extends within the insulating multilayer to emerging onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.
    Type: Application
    Filed: December 8, 2015
    Publication date: December 22, 2016
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Emmanuel Petitprez
  • Publication number: 20160260811
    Abstract: An aspect of the invention is directed to a silicon-on-insulator device including a silicon layer on an insulating layer on a substrate; a raised source and a raised drain on the silicon layer; a gate between the raised source and the raised drain; a first spacer separating the gate from the raised source and substantially covering a first sidewall of the gate; a second spacer separating the gate from the raised drain and substantially covering a second sidewall of the gate; and a low-k layer over the raised source, the raised drain, the gate and each of the first spacer and the second spacer; and a dielectric layer over the low-k layer.
    Type: Application
    Filed: March 5, 2015
    Publication date: September 8, 2016
    Inventors: Ahmet S. Ozcan, Emmanuel Petitprez
  • Patent number: 8848417
    Abstract: A structure for storing a native binary code in an integrated circuit, including an array of planar MIM capacitors above an insulating layer formed above a copper metallization network, wherein at least one metallization portion is present under each MIM capacitor. The size of the portion(s) is selected so that from 25 to 75% of the MIM capacitors have a breakdown voltage smaller by at least 10% than that of the other MIM capacitors.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: September 30, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Emmanuel Petitprez
  • Publication number: 20130083586
    Abstract: A structure for storing a native binary code in an integrated circuit, including an array of planar MIM capacitors above an insulating layer formed above a copper metallization network, wherein at least one metallization portion is present under each MIM capacitor. The size of the portion(s) is selected so that from 25 to 75% of the MIM capacitors have a breakdown voltage smaller by at least 10% than that of the other MIM capacitors.
    Type: Application
    Filed: September 7, 2012
    Publication date: April 4, 2013
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Emmanuel Petitprez
  • Patent number: 8202798
    Abstract: An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterized in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: June 19, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Greg Braeckelmann, Hisao Kawasaki, Marius Orlowski, Emmanuel Petitprez
  • Publication number: 20100314769
    Abstract: An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterised in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.
    Type: Application
    Filed: September 20, 2007
    Publication date: December 16, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Greg Braeckelmann, Hisao Kawasaki, Marius Orlowski, Emmanuel Petitprez