Patents by Inventor Emmanuel Richard
Emmanuel Richard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240082363Abstract: Described herein are fixed doses and dosing regimens for long-acting insulin receptor agonists suitable for once-weekly dosing, such as weekly basal insulin-Fc (BIF).Type: ApplicationFiled: December 14, 2021Publication date: March 14, 2024Inventors: Molly Corbett CARR, Emmanuel CHIGUTSA, Jenny Y. CHIEN, Parag GARHYAN, Axel Richard Karl-August HAUPT, Cheng Cai TANG
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Patent number: 10714913Abstract: An aerial cable treatment system having a cable surface preparation assembly and a coating assembly. The cable treatment system is translatable along an in-situ aerial cable. The cable surface preparation assembly can remove dirt and debris, such as carbon deposit, grease, mud, fertilizers, bird droppings, fungal growth, mosses, soot, ice, and like from aerial cables with varying sizes as it translates along the cable. The coating assembly can apply a coating to the outer surface of the in-situ aerial cable it translates along the cable.Type: GrantFiled: June 6, 2018Date of Patent: July 14, 2020Assignee: GENERAL CABLE TECHNOLOGIES CORPORATIONInventors: William Shawn Temple, Sathish Kumar Ranganathan, Gordon Carl Baker, Srinivas Siripurapu, Emmanuel Richards Stephen Joseph, Rajesh Sangalge, Sundaresan Poovalingam, Veera Venkata Ravi Kumar Geddam
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Patent number: 10461512Abstract: An aerial cable treatment system having a cable surface preparation assembly and a coating assembly. The cable treatment system is translatable along an in-situ aerial cable. The cable surface preparation assembly can remove dirt and debris, such as carbon deposit, grease, mud, fertilizers, bird droppings, fungal growth, mosses, soot, ice, and like from aerial cables with varying sizes as it translates along the cable. The coating assembly can apply a coating to the outer surface of the in-situ aerial cable it translates along the cable.Type: GrantFiled: May 9, 2018Date of Patent: October 29, 2019Assignee: GENERAL CABLE TECHNOLOGIES CORPORATIONInventors: William Shawn Temple, Sathish Kumar Ranganathan, Gordon Carl Baker, Srinivas Siripurapu, Emmanuel Richards Stephen Joseph, Rajesh Sangalge, Sundaresan Poovalingam, Veera Venkata Ravi Kumar Geddam
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Patent number: 10381344Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.Type: GrantFiled: February 15, 2018Date of Patent: August 13, 2019Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Olivier Weber, Emmanuel Richard, Philippe Boivin
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Patent number: 10332808Abstract: A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.Type: GrantFiled: February 14, 2018Date of Patent: June 25, 2019Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS (CROLLES 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Franck Julien, Stephan Niel, Emmanuel Richard, Olivier Weber
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Publication number: 20180331516Abstract: An aerial cable treatment system having a cable surface preparation assembly and a coating assembly. The cable treatment system is translatable along an in-situ aerial cable. The cable surface preparation assembly can remove dirt and debris, such as carbon deposit, grease, mud, fertilizers, bird droppings, fungal growth, mosses, soot, ice, and like from aerial cables with varying sizes as it translates along the cable. The coating assembly can apply a coating to the outer surface of the in-situ aerial cable it translates along the cable.Type: ApplicationFiled: June 6, 2018Publication date: November 15, 2018Inventors: William Shawn Temple, Sathish Kumar Ranganathan, Gordon Carl Baker, Srinivas Siripurapu, Emmanuel Richards Stephen Joseph, Rajesh Sangalge, Sundaresan Poovalingam, Veera Venkata Ravi Kumar Geddam
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Publication number: 20180331515Abstract: An aerial cable treatment system having a cable surface preparation assembly and a coating assembly. The cable treatment system is translatable along an in-situ aerial cable. The cable surface preparation assembly can remove dirt and debris, such as carbon deposit, grease, mud, fertilizers, bird droppings, fungal growth, mosses, soot, ice, and like from aerial cables with varying sizes as it translates along the cable. The coating assembly can apply a coating to the outer surface of the in-situ aerial cable it translates along the cable.Type: ApplicationFiled: May 9, 2018Publication date: November 15, 2018Inventors: William Shawn Temple, Sathish Kumar Ranganathan, Gordon Carl Baker, Srinivas Siripurapu, Emmanuel Richards Stephen Joseph, Rajesh Sangalge, Sundaresan Poovalingam, Veera Venkata Ravi Kumar Geddam
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Publication number: 20180269115Abstract: A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.Type: ApplicationFiled: February 14, 2018Publication date: September 20, 2018Inventors: Franck Julien, Stephan Niel, Emmanuel Richard, Olivier Weber
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Publication number: 20180175022Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.Type: ApplicationFiled: February 15, 2018Publication date: June 21, 2018Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Olivier Weber, Emmanuel Richard, Philippe Boivin
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Patent number: 9929146Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.Type: GrantFiled: March 9, 2017Date of Patent: March 27, 2018Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Olivier Weber, Emmanuel Richard, Philippe Boivin
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Publication number: 20170317106Abstract: An integrated circuit is formed using a substrate of a silicon-on-insulator type that includes a carrier substrate and a stack of a buried insulating layer and a semiconductor film on the carrier substrate. A first region without the stack separates a second region that includes the stack from a third region that also includes the stack. An MOS transistor has a gate dielectric region formed by a portion of the buried insulating layer in the second region and a gate region formed by a portion of the semiconductor film in the second region. The carrier substrate incorporates doped regions under the first region which form at least a part of a source region and drain region of the MOS transistor.Type: ApplicationFiled: November 28, 2016Publication date: November 2, 2017Applicants: STMicroelectronics (Rousset 2) SAS, STMicroelectronics (Crolles 2) SASInventors: Philippe Boivin, Franck Arnaud, Gregory Bidal, Dominique Golanski, Emmanuel Richard
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Publication number: 20170271325Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.Type: ApplicationFiled: March 9, 2017Publication date: September 21, 2017Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Olivier Weber, Emmanuel Richard, Philippe Boivin
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Publication number: 20160099183Abstract: The transverse mechanical stress within the active region of a MOS transistor is relaxed by forming an insulating incursion, such as an insulated trench, within the active region of the MOS transistor. The insulated incursion is provided at least in a channel region of the MOS transistor so as to separate the channel region into two parts. The insulated incursion is configured to extend in a direction of a length of the MOS transistor. The insulated incursion may further extend into one or more of a source region or drain region located adjacent the channel region of the MOS transistor.Type: ApplicationFiled: December 11, 2015Publication date: April 7, 2016Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Denis Rideau, Elise Baylac, Emmanuel Richard, Francois Andrieu
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Publication number: 20150097241Abstract: The transverse mechanical stress within the active region of a MOS transistor is relaxed by forming an insulating incursion, such as an insulated trench, within the active region of the MOS transistor. The insulated incursion is provided at least in a channel region of the MOS transistor so as to separate the channel region into two parts. The insulated incursion is configured to extend in a direction of a length of the MOS transistor. The insulated incursion may further extend into one or more of a source region or drain region located adjacent the channel region of the MOS transistor.Type: ApplicationFiled: October 3, 2014Publication date: April 9, 2015Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Denis Rideau, Elise Baylac, Emmanuel Richard, Francois Andrieu
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Patent number: 8877600Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.Type: GrantFiled: December 12, 2013Date of Patent: November 4, 2014Assignees: STMicroelectronics, Inc., STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Claire Fenouillet-Beranger, Stephane Denorme, Nicolas Loubet, Qing Liu, Emmanuel Richard, Pierre Perreau
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Publication number: 20140170834Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.Type: ApplicationFiled: December 12, 2013Publication date: June 19, 2014Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat à l'Énergie Atomique et aux Énergies Alternatives, STMicroelectronics, Inc., STMicroelectronics S.A.Inventors: Claire Fenouillet-Beranger, Stephane Denorme, Nicolas Loubet, Qing Liu, Emmanuel Richard, Pierre Perreau
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Patent number: 6495453Abstract: The present invention is related to a method for depositing a metal-containing film from a metal plating bath, comprising the steps of subsequently depositing a metal-containing layer from a metal plating bath followed by a heating step and/or a vacuum step, said subsequent steps being repeated for a number of times in different sequences.Type: GrantFiled: June 22, 2000Date of Patent: December 17, 2002Assignee: Interuniversitair Microelectronica CentrumInventors: Sywert H. Brongersma, Emmanuel Richard, Iwan Vervoort, Karen Maex