Patents by Inventor Emmanuel Solari

Emmanuel Solari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit with input and/or output bolton pads with integrated logic
    Patent number: 7928760
    Abstract: An input and/or output pad is dedicated to an integrated circuit comprising a core with input and/or output pins. This pad comprises a pad cell comprising a pad block connected to an input buffer and/or an output buffer and arranged to be connected to one of the core input and/or output pins. The pad also comprises a pad logic module comprising a first and/or a second boundary scan cell, connected to the pad block through the input buffer and/or output buffer and arranged to feed input signals to and/or deliver output signals from the pad block, and control means connected to the first and/or second boundary scan cell(s) and adapted to receive control signals for controlling access to the first and/or second boundary scan cell(s) and feeding the first boundary scan cell with the input signals and/or outputting the output signals delivered by the first boundary scan cell.
    Type: Grant
    Filed: September 5, 2005
    Date of Patent: April 19, 2011
    Assignee: NXP B.V.
    Inventors: Eric Bernasconi, Emmanuel Solari
  • INTEGRATED CIRCUIT WITH INPUT AND/OR OUTPUT BOLTON PADS WITH INTEGRATED LOGIC
    Publication number: 20090201049
    Abstract: An input and/or output pad (P) is dedicated to an integrated circuit comprising a core with input and/or output pins. This pad (P) comprises a pad cell (PC) comprising a pad block (PB) connected to an input buffer (IB1, IB2) and/or an output buffer (OB) and arranged to be connected to one of the core input and/or output pins. The pad (P) also comprises a pad logic module (PLM) comprising a first boundary scan cell (BC1) and/or a second boundary scan cell (BC2), connected to the pad block (PB) through the input buffer (IB1, IB2) and/or output buffer (OB) and arranged to feed input signals to and/or deliver output signals from the pad block (PB), and control means connected to the first (BC1) and/or second (BC2) boundary scan cell(s) and adapted to receive control signals for controlling access to the first and/or second boundary scan cell(s) and feeding the first boundary scan cell (BC1) with the input signals and/or outputting the output signals delivered by the first boundary scan cell (BC 1).
    Type: Application
    Filed: September 5, 2005
    Publication date: August 13, 2009
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Eric Bernasconi, Emmanuel Solari
  • Method of testing an integrated circuit by simulation
    Publication number: 20030128022
    Abstract: The present invention relates to an integrated circuit test method, said method using at least one test vector comprising serialized input (SHIFT_IN) and output values.
    Type: Application
    Filed: December 20, 2002
    Publication date: July 10, 2003
    Inventors: Laurent Souef, Emmanuel Solari, Soenke Rogge, Rainer Kytzia, Michael Wittke