Abstract: A touch sensor panel comprises a plurality of touch electrodes in a two-dimensional array, the plurality of touch electrodes including first and second touch electrodes disposed along a first axis. The first and second touch electrodes can each include one or more first protrusions along a first side and one or more second protrusions along a second side, opposite the first side. The one or more first protrusions along the first side can be offset along a second axis, orthogonal to the first axis, from the one or more second protrusions along the second side. The first and second touch electrodes can tessellate such that the one or more first protrusions along the first side of the first touch electrode interlock with the one or more second protrusions along the second side of the second touch electrode.

Abstract: In one example in accordance with the present disclosure a memristive bit cell is described. The memristive bit cell includes a memristive device switchable between states. The memristive device is to store information. The memristive bit cell also includes a first switch regulating component coupled to the memristive device. The first switch regulating component enforces compliance of the memristive device with a first property threshold when switching between states in a first direction. The first property threshold corresponds to a state of the memristive device. The memristive bit cell also includes a second switch regulating component coupled to the memristive device. The second switch regulating component enforces compliance of the memristive device with a second property threshold when switching between states in a second direction. The second property threshold corresponds to a state of the memristive device.

Abstract: In one example in accordance with the present disclosure a memristive bit cell is described. The memristive bit cell includes a memristive device switchable between states. The memristive device is to store information. The memristive bit cell also includes a first switch regulating component coupled to the memristive device. The first switch regulating component enforces compliance of the memristive device with a first property threshold when switching between states in a first direction. The first property threshold corresponds to a state of the memristive device. The memristive bit cell also includes a second switch regulating component coupled to the memristive device. The second switch regulating component enforces compliance of the memristive device with a second property threshold when switching between states in a second direction. The second property threshold corresponds to a state of the memristive device.

Abstract: An optical attenuator (104) includes a substrate (116), an attenuation layer (120), and a pair of electrodes (124). The substrate (116) is transparent with respect to a range of light wavelengths. The attenuation layer (120) is formed on the substrate (116) and includes a strongly-correlated material. An optical transmissivity of the strongly-correlated material is strongly correlated with a resistance of the strongly-correlated material, and the optical transmissivity as applied to the light wavelengths is variable. The pair of electrodes (124) is at least one of formed on and embedded within the attenuation layer (120). The pair of electrodes (124) is configured to provide an indication of the resistance of the attenuation layer (120).

Abstract: An example device in accordance with an aspect of the present disclosure includes at least one current comparator, a plurality of threshold currents, and a controller. The current comparator is to compare a memristor current to a plurality of threshold currents. The controller is to set a desired memristance state of a memristor according to a memristance feedback tuning loop based on a plurality of threshold levels. The controller is to apply positive and negative voltages to the memristor during the feedback tuning loop to achieve the desired memristance state of the memristor.

Abstract: Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column line and a row line of the RRAM array. A first column line may be coupled to a first input of a first current-steering multiplexer and the first current-steering multiplexer may have an output coupled to a first current sense amplifier and a select input coupled to a first column select signal. A second column line may be coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer. The second current-steering multiplexer may have an output coupled to a second current sense amplifier and a select input coupled to a second column select signal. A third column line may be coupled to a second input of the second current-steering multiplexer.

Abstract: An example device in accordance with an aspect of the present disclosure includes at least one current comparator, a plurality of threshold currents, and a controller. The current comparator is to compare a memristor current to a plurality of threshold currents. The controller is to set a desired memristance state of a memristor according to a memristance feedback tuning loop based on a plurality of threshold levels. The controller is to apply positive and negative voltages to the memristor during the feedback tuning loop to achieve the desired memristance state of the memristor.

Abstract: Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column line and a row line of the RRAM array. A first column line may be coupled to a first input of a first current-steering multiplexer and the first current-steering multiplexer may have an output coupled to a first current sense amplifier and a select input coupled to a first column select signal. A second column line may be coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer. The second current-steering multiplexer may have an output coupled to a second current sense amplifier and a select input coupled to a second column select signal. A third column line may be coupled to a second input of the second current-steering multiplexer.

Abstract: A set procedure of a one transistor, one memristor memory elements may comprise determining a gate voltage for the transistor based on the desired target value. Increasing set pulses may be applied to memristor while the gate is held at the determined gate voltage.

Abstract: Memristive computation of a cross product is disclosed. One example is a crossbar array of memory elements that include a number of column lines perpendicular to a number of row lines, a memory element located at each intersection of a row line and a column line. A programming voltage is applied at each memory element to change a resistance value to represent a respective entry in a skew symmetric matrix representing a first vector, and an input voltage is applied along each row line to represent a dimensional component of a second vector. Sensors located at each column line measure output voltages along column lines, where the output voltages are generated by applying input voltages received by memory elements located along the row line to resistance values of the respective memory elements. Differential amplifiers collate the output voltages for pairs of sensors to generate dimensional components of the cross product.

Abstract: A method of operating a plurality of memristive cells coupled as a memristor array includes initializing a first select line, and, in parallel for a number of memristor cells in the first select line, determining whether a level of conductance of the memristor cells in the first select line are within a tolerance of a reference conductance, and, in response to a determination that the level of conductance is not within the tolerance of the reference conductance, adjusting the level of conductance for the memristor cells in the first select line.

Abstract: An optical attenuator (104) includes a substrate (116), an attenuation layer (120), and a pair of electrodes (124). The substrate (116) is transparent with respect to a range of light wavelengths. The attenuation layer (120) is formed on the substrate (116) and includes a strongly-correlated material. An optical transmissivity of the strongly-correlated material is strongly correlated with a resistance of the strongly-correlated material, and the optical transmissivity as applied to the light wavelengths is variable. The pair of electrodes (124) is at least one of formed on and embedded within the attenuation layer (120). The pair of electrodes (124) is configured to provide an indication of the resistance of the attenuation layer (120).