Abstract: A processing unit and a method of operating a processing unit. In an embodiment, the processing unit comprises a SIMON block cipher for transforming plaintext data into encrypted data. A key expansion module generates and outputs one or more encryption keys; and the key expansion module includes a first series of adiabatic registers for holding key generation data values, and for using adiabatic switching to transmit the key generation data values through the first series of adiabatic registers. A round function module receives the plaintext data and the one or more encryption keys, encrypts the plaintext data to generate the encrypted data, and outputs the encrypted data; and the round function module includes a second series of adiabatic registers for holding encryption data, and for using adiabatic switching to transmit the encryption data through the second series of adiabatic registers.

Abstract: A processing unit and a method of operating a processing unit. In an embodiment, the processing unit comprises a SIMON block cipher for transforming plaintext data into encrypted data. A key expansion module generates and outputs one or more encryption keys; and the key expansion module includes a first series of adiabatic registers for holding key generation data values, and for using adiabatic switching to transmit the key generation data values through the first series of adiabatic registers. A round function module receives the plaintext data and the one or more encryption keys, encrypts the plaintext data to generate the encrypted data, and outputs the encrypted data; and the round function module includes a second series of adiabatic registers for holding encryption data, and for using adiabatic switching to transmit the encryption data through the second series of adiabatic registers.

Abstract: Provided is a passive charge recovery logic circuit that includes an electromagnetic field capturing device that harvests ambient electromagnetic energy, with the device including a first end and a second end; a first phase shifter including a first end connected to the first end of the device; a second phase shifter including a first end connected to the second end of the device; a peak detector including a first end connected to the first end of the device; and at least four gates that operate by respective first to fourth power clock signals.

Abstract: Provided is a passive charge recovery logic circuit that includes an electromagnetic field capturing device that harvests ambient electromagnetic energy, with the device including a first end and a second end; a first phase shifter including a first end connected to the first end of the device; a second phase shifter including a first end connected to the second end of the device; a peak detector including a first end connected to the first end of the device; and at least four gates that operate by respective first to fourth power clock signals.

Abstract: A system for performing slew-driven clock tree synthesis includes pair selection and cost metric definition considering physical distance for efficient sink clustering; slew and skew-aware merging point computation for routing; and slew and insertion slew-aware net splitting.

Abstract: A system for performing slew-driven clock tree synthesis includes pair selection and cost metric definition considering physical distance for efficient sink clustering; slew and skew-aware merging point computation for routing; and slew and insertion slew-aware net splitting.

Abstract: Apparatus and a method are provided for reducing noise in mixed-signal and digital circuits. One apparatus (200) includes a metal-oxide-semiconductor field-effect transistor (MOSFET) (210). MOSFET (210) includes a doped substrate (2210) with a source formed proximate a substrate tie (2224) and a substrate tie (2250) adjacent substrate (2210). A ground rail (255) is coupled to the source and substrate tie (2224), and a ground rail (285) is coupled to substrate tie (2250). Ground rails (255) and (285) are configured to be coupled to different ground networks (250 and 280). One method includes producing a model of a semiconductor device including a standard semiconductor cell (710). The semiconductor cell is identified as a noise-sensitive or a noise-producing semiconductor cell (720), and the semiconductor cell is replaced with a corresponding noise-aware semiconductor cell (730).

Abstract: A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews calculated for each synchronous circuit are compared with a selected setup/hold time pair stored in the cell library (e.g., a pair having a relatively low hold value). If at least one of the setup and hold skews violates the selected setup/hold time pair, then the remaining identified setup/hold time pairs (or the PWL approximation) are utilized to determine if the synchronous circuit is violates established constraints, and if not, to identify the setup and hold times required to remove the violation.

Abstract: A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews calculated for each synchronous circuit are compared with a selected setup/hold time pair stored in the cell library (e.g., a pair having a relatively low hold value). If at least one of the setup and hold skews violates the selected setup/hold time pair, then the remaining identified setup/hold time pairs (or the PWL approximation) are utilized to determine if the synchronous circuit is violates established constraints, and if not, to identify the setup and hold times required to remove the violation.

Abstract: A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews calculated for each synchronous circuit are compared with a selected setup/hold time pair stored in the cell library (e.g., a pair having a relatively low hold value). If at least one of the setup and hold skews violates the selected setup/hold time pair, then the remaining identified setup/hold time pairs (or the PWL approximation) are utilized to determine if the synchronous circuit is violates established constraints, and if not, to identify the setup and hold times required to remove the violation.

Abstract: Apparatus and a method are provided for reducing noise in mixed-signal and digital circuits. One apparatus (200) includes a metal-oxide-semiconductor field-effect transistor (MOSFET) (210). MOSFET (210) includes a doped substrate (2210) with a source formed proximate a substrate tie (2224) and a substrate tie (2250) adjacent substrate (2210). A ground rail (255) is coupled to the source and substrate tie (2224), and a ground rail (285) is coupled to substrate tie (2250). Ground rails (255) and (285) are configured to be coupled to different ground networks (250 and 280). One method includes producing a model of a semiconductor device including a standard semiconductor cell (710). The semiconductor cell is identified as a noise-sensitive or a noise-producing semiconductor cell (720), and the semiconductor cell is replaced with a corresponding noise-aware semiconductor cell (730).

Abstract: A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews selected setup/hold time pair stored in the cell library (e.g., a pair having a relatively low hold value). If at least one of the setup and hold skews violates the selected setup/hold time pair, then the remaining identified setup/hold time pairs (or the PWL approximation) are utilized to determine if the synchronous circuit is violates established constraints, and if not, to identify the setup and hold times required to remove the violation.