Abstract: Apparatuses and methods of operating apparatuses are disclosed. An apparatus comprises a flexible substrate and circuitry fabricated on the flexible substrate to perform data processing. At least one strain detector generates a strain signal which is dependent on a flexing state of the strain detector on the flexible substrate. A strain history control unit samples the at least one strain signal from the at least one strain detector at a plurality of time points and records a strain snapshot at each time point comprising data dependent on the at least one strain signal from the at least one strain detector. The data processing performed by the circuitry is dependent on the plurality of strain snapshots recorded.

Abstract: Battery cell monitoring systems comprising a flexible substrate and components integrated onto the flexible substrate, and methods of operating the same are disclosed. The components comprise a computing device and at least one sensor, where the at least one sensor is configured to generate sensor signals indicative of a physical state of the battery cell. The computing device is configured to hold characteristic data values which have been generated based on prior sensor signals. The computing device is configured to receive the sensor signals from the at least one sensor and to generate battery cell status data in dependence on the sensor signals and the characteristic data values.

Abstract: Packaging for a pharmaceutical product and a method of validating pharmaceuticals is disclosed. The packaging comprising a cavity; and validation circuitry comprising: a sensor adapted to output a signal in response to detecting a vapour in the cavity; and a detection circuit adapted to output an indication when the signal indicates a predefined vapour signature.

Abstract: Aspects of the present disclosure relate to an apparatus comprising: a substrate; communication circuitry deposited on said substrate; and ballot circuitry deposited on said substrate. The ballot circuitry comprises: a plurality of voting circuitry elements, each voting circuitry element being responsive to a voting operation to change a conductive state of that voting circuitry element; and logic circuitry communicatively coupled with each of the plurality of voting circuitry elements and with the communication circuitry. The logic circuitry is configured to: detect the conductive state of each of the plurality of voting circuitry elements; and transmit, via the communication circuitry and based on the conductive state of each of the plurality of voting circuitry elements, a voting result.

Abstract: Apparatus comprises at least one visual indicator element; at least one detector to detect access to the apparatus consistent with a cleaning operation being applied to a surface of the apparatus; and processing circuitry to control a visual indication state of the at least one visual indicator element in response to a detection by the detector of access to the surface of the apparatus.

Abstract: Aspects of the present disclosure relate to an apparatus comprising: a substrate; communication circuitry deposited on said substrate; and ballot circuitry deposited on said substrate. The ballot circuitry comprises: a plurality of voting circuitry elements, each voting circuitry element being responsive to a voting operation to change a conductive state of that voting circuitry element; and logic circuitry communicatively coupled with each of the plurality of voting circuitry elements and with the communication circuitry. The logic circuitry is configured to: detect the conductive state of each of the plurality of voting circuitry elements; and transmit, via the communication circuitry and based on the conductive state of each of the plurality of voting circuitry elements, a voting result.

Abstract: An apparatus comprises a plurality of redundant processing units to perform data processing redundantly in lockstep; common mode fault detection circuitry to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory shared between the plurality of redundant processing units; and memory checking circuitry to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry indicating that the event indicative of a potential common mode fault has been detected.

Abstract: Data processing apparatus having a binary neural network, BNN, circuitry to implement a BNN; the BNN circuitry having at least one instance of hidden layer circuitry responsive to trained one-bit weight values and input data values to generate a hidden layer output signal; each input data value has a one-hot n-bit data value, where n is an integer greater than one; the hidden layer circuitry is configured to generate the hidden layer output signal dependent upon an intermediate result of a selective inversion operation applied to each bit of a given input data value; the hidden layer circuitry has circuitry to generate a respective intermediate result as a first predetermined result value for the given input data value; and, for a group of trained one-bit weight values, circuitry to generate a respective intermediate result as a second predetermined result value for the given input data value.

Abstract: Apparatuses and methods of operating apparatuses are disclosed. An apparatus comprises a flexible substrate and circuitry fabricated on the flexible substrate to perform data processing. At least one strain detector generates a strain signal which is dependent on a flexing state of the strain detector on the flexible substrate. A strain history control unit samples the at least one strain signal from the at least one strain detector at a plurality of time points and records a strain snapshot at each time point comprising data dependent on the at least one strain signal from the at least one strain detector.

Abstract: Smart labels, methods of operating smart labels, and associated contexts in which such smart labels may be used are disclosed. The smart label, for use in conjunction with consumer product packaging, comprises an energy harvester to capture ambient energy to provide a source of electrical energy and electronic circuitry powered by the electrical energy. A fuse provides an electrical connection between the energy harvester and the electronic circuitry and destruction of the fuse permanently disconnects the energy harvester from the electronic circuitry. Unnecessary continued operation of the electronic circuitry powered by the energy harvester can therefore be prevented, for example when the consumer product packaging is disposed of or recycled, which may be an undesirable heat source. Smart labelling, and a connected network of smart bins which can read the smart labelling, may also be used to promote consumer recycling of consumer product packaging.

Abstract: Apparatuses and methods of operating such apparatuses are disclosed. An apparatus comprises feature dataset input circuitry to receive a feature dataset comprising multiple feature data values indicative of a set of features, wherein each feature data value is represented by a set of bits. Class retrieval circuitry is responsive to reception of the feature dataset from the feature dataset input circuitry to retrieve from class indications storage a class indication for each feature data value received in the feature dataset, wherein class indications are predetermined and stored in the class indications storage for each permutation of the set of bits for each feature. Classification output circuitry is responsive to reception of class indications from the class retrieval circuitry to determine a classification in dependence on the class indications. A predicated class may thus be accurately generated from a simple apparatus.

Abstract: Apparatuses, methods of operating apparatuses, and corresponding computer programs are disclosed. In the apparatuses input circuitry receives input data comprising at least one data element and shift circuitry generates, for each data element of the input data, a bit-map giving a one-hot encoding representation of the data element, wherein a position of a set bit in the bit-map is dependent on the data element. Summation circuitry generates a position summation value for each position in the bit-map, wherein each position summation value is a sum across all bit-maps generated by the shift circuitry from the input data. Maximum identification circuitry determines at least one largest position summation value generated by the summation circuitry and output circuitry to generate an indication of at least one data element corresponding to the at least one largest position summation value. The statistical mode of the data elements in the input data is thereby efficiently determined.

Abstract: An apparatus comprises a plurality of redundant processing units (4) to perform data processing redundantly in lockstep; common mode fault detection circuitry *6, 22) to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory (10) shared between the plurality of redundant processing units; and memory checking circuitry (30) to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry (30) performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry (6, 22) indicating that the event indicative of a potential common mode fault has been detected.

Abstract: Apparatuses, methods of operating apparatuses, and corresponding computer programs are disclosed. In the apparatuses input circuitry receives input data comprising at least one data element and shift circuitry generates, for each data element of the input data, a bit-map giving a one-hot encoding representation of the data element, wherein a position of a set bit in the bit-map is dependent on the data element. Summation circuitry generates a position summation value for each position in the bit-map, wherein each position summation value is a sum across all bit-maps generated by the shift circuitry from the input data. Maximum identification circuitry determines at least one largest position summation value generated by the summation circuitry and output circuitry to generate an indication of at least one data element corresponding to the at least one largest position summation value. The statistical mode of the data elements in the input data is thereby efficiently determined.

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry to execute a plurality of code sequences, and configuration storage to store mode control data for the processing circuitry. When the processing circuitry is executing one of said plurality of code sequences, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry.

Abstract: A method for estimating a number of occupants in a region comprises receiving a time series of sensor values detected over a period of time by a motion sensor sensing motion in the region. A spread parameter indicative of the spread of the sensor values is determined. The number of occupants in the region is estimated based on the spread parameter.

Abstract: An apparatus and method are provided for checking output data during redundant execution of instructions. The apparatus has first processing circuitry for executing a sequence of instructions and second processing circuitry for redundantly executing the sequence of instructions. Error code generation circuitry is used to generate an error code from the first output data generated by the first processing circuitry. Error checking circuitry then uses that error code to perform an error checking operation on redundant output data from the second processing circuitry. As a result of the error checking operation, the error checking circuitry then generates a comparison indication signal to indicate that the first output data differs from the redundant output data when the error checking operation detects an error. This provides a very efficient mechanism for implicitly comparing the output data from the first processing circuitry and the second processing circuitry during redundant execution.

Abstract: An apparatus and method are provided for increasing resilience to faults. The apparatus comprises processing circuitry for executing a plurality of code sequences including at least one critical code sequence, and configuration storage for storing mode control data for the processing circuitry. When the processing circuitry is executing a critical code sequence, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry, where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry. By increasing the resilience to faults, this reduces the chance that any such fault will manifest itself as an error in the processing operations being performed by the apparatus.

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry to execute a plurality of code sequences, and configuration storage to store mode control data for the processing circuitry. When the processing circuitry is executing one of said plurality of code sequences, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry.

Abstract: An apparatus comprises at least three processing circuits to perform redundant processing of common program instructions. Error detection circuitry coupled to a plurality of signal nodes of each of said at least three processing circuits comprises comparison circuitry to detect a mismatch between signals on corresponding signal nodes in said at least three processing circuits, the plurality of signal nodes forming a first group of signal nodes and a second group of signal nodes. In response to the mismatch being detected in relation to corresponding signal nodes within the first group, the error detection circuitry is configured to generate a first trigger for a full recovery process for resolving an error detected for an erroneous processing circuit using state information derived from at least two other processing circuits.