Abstract: A direct memory access (DMA) controller is provided for a computer system having a processor and a command buffer. The command buffer can be defined, for example, as a ring buffer in the main processor memory and can be directly accessible by the processor, for example over a bus. The DMA controller provides a head register and a tail register operable to hold a head pointer and a tail pointer for addressing the head and tail, respectively, of a sequence of direct memory access commands in the command buffer. The processor is able to store DMA commands in the command buffer. Subsequently, the DMA controller is able to access those DMA commands using the DMA tail pointer held locally in the DMA controller. The DMA controller is operable to compare the head and tail pointers, and to respond to non-equivalence thereof to use the tail pointer value to access direct memory access commands from the command buffer.

Abstract: A fault tolerant computer system includes a number of lockstep subsystems, each of which comprises a parallel input signature generator, used for data compression to allow practical comparison of the operation of internal modules of the lockstep subsystem, and a logic analyzer which stores the outputs of the internal modules of the lockstep subsystem. A signature comparator is connected to receive the signatures from the signature generators of the individual lockstep subsystems. The signature comparator generates a trigger signal for triggering the logic analyzers on detecting a difference in the signatures. The logic analyzers store enough states to include the first difference from a module following a detected difference in the signature outputs. The logic analyzer traces are searched automatically after an out-of-sync event to locate the first difference in operation and to determine which internal module provided the faulty output and then that module is labelled as broken.

Abstract: A method and apparatus provides data transmission between synchronous systems. One system has a phase locked loop to provide its local clock. The other system has a fixed clock. Fully synchronous bidirectional communication is achieved by adjusting the lengths of the delays between the systems, possibly by adjusting the cable lengths. Deterministic lockstep operation between systems separated by a significant distance is permitted where the communication delays are large compared to a single clock cycle of the systems. Practical tolerances on cable length and signal noise and jitter can be accommodated.

Abstract: An arrangement is provided whereby an expansion card can be inserted in a multi-contact computer backplane connector and then gates provided between bus lines and respective connector contacts can be enabled. Hot insertability of the card and improved fault protection results. A plurality of gate signals for respective connectors can be provided so that a bus controller can selectively supply a gate signal for enabling transmission gates of only one connector for a given bus cycle, thereby providing dynamic cycle switching of the cards. The transmission gates can be provided in a backplane connector for a card. Preferably, a power supply signal is supplied to a switch gate connected between a power line and a power contact of the connector when a card has been inserted in a connector such that power is only supplied to the card only after insertion. A bus request signal can be enabled after a predetermined delay following the supply of power to the card.

Abstract: A memory management system for a fault tolerant computer system. The memory management system includes a first recording mechanism which can be activated to record memory update events; a second recording mechanism which records at least a limited number of memory update events; a fault input for a fault signal to activate the first recording mechanism in the event of a fault event; and a memory reintegration mechanism to reintegrate at least parts of memory identified in the first and second recording mechanisms. Preferably, the recording of memory updates (writes) is not based on recording each address accessed, but rather on memory segments (pages) updated (written to). Further, a fault tolerant computer system includes a plurality of synchronous processing sets, each having a processor with internal memory and operating in lockstep, and an out of sync detector for detecting an out-of-sync-event and for generating an out-of-sync signal.

Abstract: A fault tolerant computer system includes a number of lockstep subsystems, each of which comprises a parallel input signature generator, used for data compression to allow practical comparison of the operation of internal modules of the lockstep subsystem, and a logic analyzer which stores the outputs of the internal modules of the lockstep subsystem. A signature comparator is connected to receive the signatures from the signature generators of the individual lockstep subsystems. The signature comparator generates a trigger signal for triggering the logic analyzers on detecting a difference in the signatures. The logic analyzers store enough states to include the first difference from a module following a detected difference in the signature outputs. The logic analyzer traces are searched automatically after an out-of-sync event to locate the first difference in operation and to determine which internal module provided the faulty output and then that module is labelled as broken.