Patents by Inventor En Chen

En Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250255024
    Abstract: Some embodiments relate to A deep trench isolation (DTI) structure, including: a DTI core extending into a substrate; a first film surrounding the DTI core and having a first material with a first conduction band at a first band energy; a second film between the first film and the DTI core, the second film having a second material with a second conduction band at a second band energy less than the first band energy; and a third film between the second film and the DTI core, the third film having a third material with a third conduction band at a third band energy greater than the second band energy.
    Type: Application
    Filed: February 6, 2024
    Publication date: August 7, 2025
    Inventors: Bing Cheng You, Feng-Chi Hung, Wen-I Hsu, Ming-En Chen, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20250246902
    Abstract: An apparatus includes a solid state circuit breaker selectively configured as a closed switch or an open switch. A current sensor is coupled to a current path passing through the closed switch and configured to sense an electrical current flowing on the current path while the switch is closed. A student convolutional neural network (CNN) model is pretrained using a knowledge distillation-based teacher-student approach. The student CNN model is coupled to the solid state circuit breaker and the current sensor and configured to process data representative of the electrical current, the data being processed cyclically with a period defined by an arc fault detection cycle. According to some aspects, in response to the student CNN model detecting, in association with the electrical current, an arc fault lasting a predetermined number of consecutive arc fault detection cycles, the solid state circuit breaker is reconfigured as the open switch.
    Type: Application
    Filed: January 30, 2025
    Publication date: July 31, 2025
    Inventors: Tiefu ZHAO, Kamal Chandra PAUL, Shen En CHEN
  • Publication number: 20250116713
    Abstract: The present invention discloses a method of estimating a state of charge (SOC) of a battery and a system thereof. The method of estimating the SOC of the battery includes following steps: calculating a voltage difference (?V) using a voltaic gauge based on a battery voltage (VBAT) and an open-circuit voltage (OCV); adaptively adjusting a gain (K) using a gain control engine based on a battery current (IBAT) and a full charged capacity (FCC), wherein the gain (K) is adjusted to generate an adjusted gain (K?); generating a present SOC change (?SOC_T) using the voltaic gauge based on the voltage difference (?V) and the adjusted gain (K?); and generating a next SOC (SOC_T+1) using an accumulator based on a present SOC (SOC_T) and the present SOC change (?SOC_T).
    Type: Application
    Filed: October 8, 2024
    Publication date: April 10, 2025
    Inventors: Chieh-En CHEN, Chang-Yu HO
  • Publication number: 20250116708
    Abstract: A battery control parameter estimation system includes sensing, storage, and estimation circuits. The estimation circuit determines an operation model based on an estimated control parameter signal and a battery property signal or an internal reference information. The operation model defines a control parameter, a status parameter, and a relationship therebetween, and performs an estimation operation to generate an estimation result.
    Type: Application
    Filed: October 8, 2024
    Publication date: April 10, 2025
    Inventors: Chieh-En CHEN, Chung-Jen CHOU
  • Publication number: 20250116719
    Abstract: A method for determining the reference internal impedance of a battery includes the following steps: (a) during a sensing period, sensing a battery voltage, a battery current flowing through the battery, and a battery temperature to obtain a sensing result, thereby determining a depth of discharge (DOD); (b) in step (a), comparing the sensing result with a predetermined threshold to determine whether to accept the sensing result; (c) when the sensing result is accepted, calculating a corresponding battery internal impedance based on the sensing result and the depth of discharge; (d) performing regression analysis on the battery internal impedance and a plurality of previous battery internal impedances to obtain a moving average battery internal impedance corresponding to the depth of discharge; and (e) obtaining a corresponding reference battery internal impedance based on the moving average battery internal impedance.
    Type: Application
    Filed: September 19, 2024
    Publication date: April 10, 2025
    Inventors: Chieh-En Chen, Fu-Chi Lin, Wen-Yuan Li
  • Publication number: 20250063834
    Abstract: A polysilicon well is formed at a cross-road portion between a plurality of pixel sensors in a pixel sensor array. Moreover, the underlying oxide layer between the polysilicon well and a semiconductor layer of the pixel sensor array may be thinner than other areas of the oxide layer. The polysilicon well and the thinner oxide layer may reduce the likelihood of and/or the magnitude of lateral etching that occurs during etching of the semiconductor layer to form recesses in which a BDTI structure of the pixel sensor array is formed. Moreover, the bottom of the BDTI structure being surrounded by the polysilicon well enables a voltage bias to be applied to the BDTI structure through the polysilicon well to passivate damage that might have occurred to the semiconductor layer around the bottom of the BDTI structure.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Inventors: Chieh-En CHEN, Chen-Hsien LIN, Shyh-Fann TING, Wei-Chih WENG, Feng-Chi HUNG
  • Patent number: 12225735
    Abstract: A memory device is provided in various embodiments. The memory device, in those embodiments, has an ovonic threshold switching (OTS) selector comprising multiple layers of OTS materials to achieve a low leakage current and as well as relatively low threshold voltage for the OTS selector. The multiple layers can have at least one layer of low bandgap OTS material and at least one layer of high bandgap OTS material.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ju Li, Kuo-Pin Chang, Yu-Wei Ting, Ching-En Chen, Kuo-Ching Huang
  • Publication number: 20250029894
    Abstract: Some embodiments relate to an integrated circuit device incorporating a dual via structure for through-chip connections. The integrated circuit device includes a substrate, at least one dielectric layer disposed over a frontside surface of the substrate, and a plurality of metal layers residing in the at least one dielectric layer. The integrated circuit device also includes a first via structure and a second via structure. The first via structure includes a plurality of vias. The first via structure is electrically connected to one of the plurality of metal layers and extends through the frontside surface of the substrate. The second via structure extends from a backside surface of the substrate opposite the frontside surface into the substrate and contacts the first via structure.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Inventors: Chieh-En Chen, Chen-Hsien Lin, Shyh-Fann Ting
  • Publication number: 20250015124
    Abstract: Fabricating a metal-insulator-metal (MIM) capacitor structure includes: forming a patterned metallization layer; disposing a dielectric material on the patterned metallization layer; etching one or more deep trenches through the dielectric material to the patterned metallization layer; depositing a MIM multilayer on the dielectric material and inside the one or more deep trenches formed in the dielectric material; and fabricating at least one three-dimensional MIM (3D-MIM) capacitor comprising a portion of the MIM multilayer deposited inside at least one of the one or more deep trenches; and fabricating at least one second capacitor, including at least one shallow 3D-MIM capacitor comprising a portion of the MIM multilayer deposited inside one or more shallow trenches passing partway through the dielectric material that are shallower than the one or more deep trenches, and/or at least one two-dimensional MIM (2D-MIM) capacitor comprising a portion of the MIM multilayer deposited on the dielectric material.
    Type: Application
    Filed: July 7, 2023
    Publication date: January 9, 2025
    Inventors: Chieh-En Chen, Chen-Hsien Lin, Shyh-Fann Ting, Wei-Chih Weng, Hsing-Chih Lin, Dun-Nian Yaung
  • Publication number: 20250014987
    Abstract: An integrated chip including a semiconductor substrate having a first side and a second side, opposite the first side. A first transistor and a second transistor are along the first side of the semiconductor substrate. A dielectric structure including a plurality of dielectric layers is under the first side of the semiconductor substrate. A first metal line is within the dielectric structure. A second metal line is within the dielectric structure and under the first metal line. A first metal via extends between the first metal line and the second metal line. A through-substrate via (TSV) extends from the second side of the semiconductor substrate, through the semiconductor substrate between the first transistor and the second transistor, to the first metal line and the second metal line.
    Type: Application
    Filed: July 3, 2023
    Publication date: January 9, 2025
    Inventors: Chieh-En Chen, Chen-Hsien Lin, Shyh-Fann Ting, Hsing-Chih Lin, Dun-Nian Yaung
  • Publication number: 20250006762
    Abstract: An optical device and a method of fabricating the same are disclosed. The optical device includes a first die layer and a second die layer. The first die layer includes a first substrate having a first surface and a second surface opposite to the first surface, first and second pixel structures, an inter-pixel isolation structure disposed in the first substrate and surrounding the first and second pixel structures, and a floating diffusion region disposed in the first substrate and between the first and second pixel structures. The second die layer includes a second substrate having a third surface and a fourth surface opposite to the third surface and a pixel transistor group disposed on the third surface of the second substrate and electrically connected to the first and second pixel structures.
    Type: Application
    Filed: January 12, 2024
    Publication date: January 2, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh CHUANG, Hsin-Hung CHEN, Wen-I HSU, Peng-Chieh CHIN, Feng-Chi HUNG, Ming-En CHEN, Jen-Cheng LIU, Dun-Nian YAUNG
  • Publication number: 20240405131
    Abstract: A guard ring structure and a component structure are provided. The guard ring structure includes a first attached guard ring and a second attached guard ring. The first attached guard ring is disposed at a periphery of an active region. The second attached guard ring is disposed at a periphery of the first attached guard ring. The first attached guard ring and the second attached guard ring are each an attached guard ring, and form a stepped structure. The guard ring structure is a stepped diffusion structure for an avalanche photodiode.
    Type: Application
    Filed: August 7, 2023
    Publication date: December 5, 2024
    Inventors: CHAO-HSIN WU, CHI-EN CHEN, Natchanon Prechatavanich
  • Publication number: 20240389487
    Abstract: A device structure includes semiconductor devices located on a substrate; metal interconnect structures located in dielectric material layers overlying the semiconductor devices; and a non-Ohmic voltage-triggered switch including a first switch electrode that is electrically connected to one of the semiconductor devices through a subset of the metal interconnect structures, a second switch electrode, and a non-Ohmic switching material portion providing a non-Ohmic current-voltage characteristics and in contact with the first switch electrode and the second switch electrode. The non-Ohmic voltage-triggered switch may be used as an electrostatic discharge (ESD) switch.
    Type: Application
    Filed: May 15, 2023
    Publication date: November 21, 2024
    Inventors: Wei Ting Hsieh, Kuo-Ching Huang, Yu-Wei Ting, Ching-En Chen, Kuo-Pin Chang
  • Patent number: 12144493
    Abstract: A collection and test device for a rapid test is provided. The device comprises a test fluid accommodation part having a test fluid accommodation space, a test paper accommodation part having a test paper accommodation space, and a collection probe having a channel for the test fluid to flow out from the collection probe. The two ends of the test paper accommodation part are respectively connected to the test fluid accommodation part and the collection probe, and the test paper accommodation space communicates with the channel of the collection probe. The test fluid accommodation space and the test paper accommodation space are separated from each other by a temporary barrier. The temporary barrier can be manually removed or broken to make the test fluid accommodation space communicate with the test paper accommodation space. The device of the present invention can provide the test results conveniently and rapidly.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: November 19, 2024
    Assignee: NATIONAL DEFENSE MEDICAL CENTER
    Inventors: Jia-En Chen, Juin-Hong Cherng, Yuan-Hao Chen, Cheng-Che Liu, Cheng-Cheung Chen, Yu-Min Tsai, Chin-Hsieh Yi
  • Publication number: 20240379500
    Abstract: The problem of connecting a TSV to a BEOL metal interconnect structure without damaging the BEOL metal interconnect structure is solved by landing the TSV on a metal coupling structure formed during FEOL processing. The metal coupling structure is produced in accordance with design rules that apply to FEOL processing. The metal coupling structure may include substructures that have the composition and shape of wires in a transistor level metal interconnect and substructures that have the composition and shape of metal gate strips. The metal coupling structure may include pluralities of the substructures arrayed across the TSV landing area. The substructures that make up the metal coupling structure are connected to the BEOL metal interconnect through vias.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 14, 2024
    Inventors: Chieh-En Chen, Chen-Hsien Lin, Shyh-Fann Ting, Dun-Nian Yaung
  • Publication number: 20240355860
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a plurality of gate structures arranged along a first side of a substrate within a plurality of pixel regions. An etch block structure is arranged on the first side of the substrate between neighboring ones of the plurality of gate structures. A contact etch stop layer (CESL) is arranged on the etch block structure between the neighboring ones of the plurality of gate structures. An isolation structure is disposed between one or more sidewalls of the substrate and extends from a second side of the substrate to the first side of the substrate. The etch block structure is vertically between the isolation structure and the CESL.
    Type: Application
    Filed: July 3, 2023
    Publication date: October 24, 2024
    Inventors: Hsin-Hung Chen, Wen-I Hsu, Wei Long Chen, Ming-En Chen, Feng-Chi Hung, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20240297171
    Abstract: A semiconductor structure includes a substrate including a first region and a second region; a first device disposed in the first region and a second device disposed in the second region; a first isolation disposed in the first region, wherein the first isolation is between a first source and a first drain, a first spacer overlaps the first isolation, the first isolation is separated from the first spacer by a first gate dielectric.
    Type: Application
    Filed: April 25, 2024
    Publication date: September 5, 2024
    Inventors: JING-JUNG HUANG, CHING EN CHEN, JUNG-HUI KAO, KONG-BENG THEI
  • Patent number: 12063360
    Abstract: A prediction processing system includes a processing circuit and a reference data buffer. The processing circuit performs a first inter prediction operation upon a first prediction block in a frame to generate a first inter prediction result, and further performs a second inter prediction operation upon a second prediction block during a first period. The reference data buffer buffers a reference data derived from the first inter prediction result. The processing circuit further fetches the reference data from the reference data buffer, and performs a non-inter prediction operation according to at least the reference data during a second period, wherein the second period overlaps the first period.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: August 13, 2024
    Assignee: MEDIATEK INC.
    Inventors: Kai-Chun Lin, Chi-Hung Chen, Meng-Jye Hu, Hsiao-En Chen, Chih-Wen Yang, Chien-Wei Lin
  • Publication number: 20240243156
    Abstract: A process of forming a back side deep trench isolation structure for an image sensing device includes etching first trenches in the back side of a semiconductor substrate, lining the first trenches with dielectric, depositing passivation layers over and within the first trenches, and etching second trenches through the passivation layers into the first trenches, and filling the second trenches to form a substrate-embedded metal grid. Optionally, the bottoms of the first trenches are filled by depositing and etching a lower fill material prior to depositing the passivation layers. The method prevents the passivation layers from pinching off in a way that causes voids within the first trenches. The result is better optical performance such as increased quantum efficiency and reduced crosstalk.
    Type: Application
    Filed: January 17, 2023
    Publication date: July 18, 2024
    Inventors: Tsung Hsien Tsai, Cheng Yu Huang, Jen-Cheng Liu, Keng-Yu Chou, Ming-En Chen, Shyh-Fann Ting
  • Patent number: D1065159
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: March 4, 2025
    Inventor: En Chen