Patents by Inventor En Cheng

En Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240189633
    Abstract: Example respiratory protective devices with improved sound insulation are provided. For example, an example respiratory protective device comprises an inner shell component and a fan mounting component. In some examples, the inner shell component defines at least one acoustic insulation portion that is indented on an outer surface of the inner shell component. In some embodiments, the fan mounting component protrudes from an indented surface of the at least one acoustic insulation portion and comprising a plurality of acoustic insulation ribs.
    Type: Application
    Filed: November 28, 2023
    Publication date: June 13, 2024
    Inventors: En Yi CHEN, Hang TIAN, Da Cheng YE
  • Publication number: 20240177319
    Abstract: Many unsupervised domain adaptation (UDA) methods have been proposed to bridge the domain gap by utilizing domain invariant information. Most approaches have chosen depth as such information and achieved remarkable successes. Despite their effectiveness, using depth as domain invariant information in UDA tasks may lead to multiple issues, such as excessively high extraction costs and difficulties in achieving a reliable prediction quality. As a result, we introduce Edge Learning based Domain Adaptation (ELDA), a framework which incorporates edge information into its training process to serve as a type of domain invariant information. Our experiments quantitatively and qualitatively demonstrate that the incorporation of edge information is indeed beneficial and effective, and enables ELDA to outperform the contemporary state-of-the-art methods on two commonly adopted benchmarks for semantic segmentation based UDA tasks.
    Type: Application
    Filed: November 24, 2023
    Publication date: May 30, 2024
    Applicant: MEDIATEK INC.
    Inventors: Ting-Hsuan Liao, Huang-Ru Liao, Shan-Ya Yang, Jie-En Yao, Li-Yuan Tsao, Hsu-Shen Liu, Bo-Wun Cheng, Chen-Hao Chao, Chia-Che Chang, Yi-Chen Lo, Chun-Yi Lee
  • Patent number: 11996409
    Abstract: A semiconductor structure includes a power rail, a first source/drain feature disposed over the power rail, a via connecting the power rail to the first source/drain feature; an isolation feature disposed over the first source/drain feature, and a second source/drain feature disposed over the isolation feature, where the first and the second source/drain features are of opposite conductivity types.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Xuan Huang, Chia-En Huang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20240170225
    Abstract: This invention describes a packaging structure for roll-type (wound-type) aluminum conductive polymer capacitor element. Two protective substrates are applied to sandwich a roll-type capacitor element in between with an insulating material surrounding the capacitor element also in between the protective substrates. The protective substrates comprise electrically separated anodic conductive pad and cathodic conductive pad on their surfaces and through holes that pass through the conductive pads. The capacitor element is oriented with its axis perpendicular to the two substrates. The anodic and cathodic leads of the capacitor element pass through the through holes. An anodic external terminal is plated over the anodic conductive pad and a cathodic external terminal is plated over the cathodic conductive pad so that the anodic external terminal is electrically connected to the anodic lead and the cathodic external terminal is electrically connected to the cathodic lead.
    Type: Application
    Filed: November 22, 2022
    Publication date: May 23, 2024
    Inventors: Yu-Peng Chung, Chia-Wei Li, Wen Cheng Hsu, En-Ming Chen, Che-Chih Tsao
  • Patent number: 11967628
    Abstract: A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: April 23, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Wei Huang, Hsu-Cheng Fan, En-Jui Li
  • Patent number: 11961944
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, active devices and transparent conductive patterns. The active devices are formed on the semiconductor substrate. The transparent conductive patterns are formed over the active devices and electrically connected to the active devices. The transparent conductive patterns are made of a metal oxide material. The metal oxide material has a first crystalline phase with a prefer growth plane rich in oxygen vacancy, and has a second crystalline phase with a prefer growth plane poor in oxygen vacancy.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-En Yen, Ming-Da Cheng, Mirng-Ji Lii, Wen-Hsiung Lu, Cheng-Jen Lin, Chin-Wei Kang, Chang-Jung Hsueh
  • Patent number: 11946529
    Abstract: A sliding table assembly includes a sliding seat unit slidably mounted to a base unit. Two auxiliary sliding seats are slidably mounted to the base unit and disposed on two sides of the sliding seat unit. A connection member is connected between the auxiliary sliding seats. Two roller sets are respectively mounted to the auxiliary sliding seats. Each roller set has rollers to roll on the base unit. A driving screw rod is coupled to the sliding seat unit and embraced by the auxiliary seats. When the sliding unit is moved by the driving screw rod, it pushes the auxiliary sliding seats to slide together therewith.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: April 2, 2024
    Assignee: Toyo Automation Co., Ltd.
    Inventors: Kun-Cheng Tseng, Ming-Chi Su, En-Tzu Hsu
  • Patent number: 11948972
    Abstract: The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Xuan Huang, Chia-En Huang, Ching-Wei Tsai, Kuan-Lun Cheng, Yih Wang
  • Publication number: 20240095868
    Abstract: A watermark embedding method includes the following steps. The input video signal is received by a processing circuit. Grayscale information of a watermark signal is generated by the processing circuit according to a time series data and a predetermined plane. During a dark sate and a bright state in each of a plurality of consecutive periods, phases of the time series data are opposite and integral values of the grayscales of the predetermined plane are the same. The processing circuit embeds the watermark signal into the input video signal to generate an output video signal with the watermark information. The display panel displays an image according to the output video signal.
    Type: Application
    Filed: December 28, 2022
    Publication date: March 21, 2024
    Inventors: Yang-En WU, Wen-Rei GUO, Wei-Ming CHENG, Chao-Wei LI
  • Publication number: 20240086014
    Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The shielding layers may include shielding structures such as a conductive mesh structure and/or a transparent conductive film. The shielding structures may be actively driven or passively biased. In the active driving scheme, one or more inverting circuits may receive a noise signal from a cathode layer in the display and/or from the shielding structures, invert the received noise signal, and drive the inverted noise signal back onto the shielding structures to prevent any noise from the display from negatively impacting the performance of the touch sensors. In the passive biasing scheme, the shielding structures may be biased to a power supply voltage.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Rungrot Kitsomboonloha, Donggeon Han, Jason N Gomez, Kyung Wook Kim, Nikolaus Hammler, Pei-En Chang, Saman Saeedi, Shih Chang Chang, Shinya Ono, Suk Won Hong, Szu-Hsien Lee, Victor H Yin, Young-Jik Jo, Yu-Heng Cheng, Joyan G Sanctis, Hongwoo Lee
  • Publication number: 20240023235
    Abstract: The present disclosure provides a package device including a redistribution layer. The redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, and the conductive layer is disposed between the first dielectric layer and the second dielectric layer, wherein the redistribution layer has a test mark, the test mark includes a conductive pattern formed of the conductive layer, the conductive pattern includes a center portion and a plurality of extension portions, and the plurality of extension portions are respectively connected to the center portion.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Applicant: InnoLux Corporation
    Inventors: Yeong-E CHEN, Cheng-En CHENG, Yu-Ting LIU
  • Publication number: 20240006249
    Abstract: The present disclosure provides an electronic device including a redistribution layer, a plurality of passive components, and an electronic component. The redistribution layer includes a first insulating layer, a second insulating layer, and a plurality of traces electrically connected to each other through a first opening of the first insulating layer and a second opening of the second insulating layer, wherein the first insulating layer has a first side away from the second insulating layer, and the second insulating layer has a second side away from the first insulating layer. The passive components are disposed on the first side. The electronic component is disposed on the second side. The plurality of passive components are electrically connected to the electronic component through the plurality of traces.
    Type: Application
    Filed: September 19, 2023
    Publication date: January 4, 2024
    Applicant: InnoLux Corporation
    Inventors: Yeong-E CHEN, Kuang-Chiang HUANG, Yu-Ting LIU, Yi-Hung LIN, Cheng-En CHENG
  • Publication number: 20230395703
    Abstract: A semiconductor structure includes substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers extend in an X-direction and over the substrate. The semiconductor layers are spaced apart from each other in a Z-direction. The source/drain features are on opposite sides of the semiconductor layers in the X-direction. The metal oxide layers cover bottom surfaces of the semiconductor layers. The gate structure wraps around the semiconductor layers and the metal oxide layers. The metal oxide layers are in contact with the gate structure.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hao LIN, Chia-Hung CHOU, Chih-Hsuan CHEN, Ping-En CHENG, Hsin-Wen SU, Chien-Chih LIN, Szu-Chi YANG
  • Patent number: 11812549
    Abstract: A package device and a manufacturing method thereof are provided. The package device includes a redistribution layer. The redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, and the conductive layer is disposed between the first dielectric layer and the second dielectric layer, wherein the redistribution layer has a test mark, the test mark includes a conductive pattern formed of the conductive layer, the conductive pattern includes a center portion and a plurality of extension portions, and the plurality of extension portions are respectively connected to the center portion.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: November 7, 2023
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Cheng-En Cheng, Yu-Ting Liu
  • Patent number: 11804793
    Abstract: A method of speed control based on a self-learning model of load torque and a moment inertia is applied to a controller of controlling a motor. The method includes steps of: establishing a relationship between the load torque and the moment inertia by a self-learning manner, correspondingly acquiring a value of the moment inertia according to a value of the load torque, and adjusting parameters of the controller to control rotation of the motor according to the value of the moment inertia.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: October 31, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Shao-Kai Tseng, Pai-En Cheng, Chen-Yeh Lee
  • Patent number: 11801830
    Abstract: A control device for vehicle is provided, and includes a communicator configured to receive first image information from a camera device and a processor coupled to the communicator and configured to: extract label information in the first image information; perform edge detection on the label information and extract a total number of edges; normalize the total number of edges to form a first label clarity; and when the first label clarity is greater than or equal to a preset threshold, control the vehicle to move to a parking position according to the first image information. A control method for vehicle is also provided. The present disclosure can effectively reduce the number of starts and stops of the vehicle and shorten the parking time of the vehicle.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: October 31, 2023
    Assignee: Fulian Yuzhan Precision Technology Co., Ltd
    Inventor: Hao-En Cheng
  • Patent number: 11798853
    Abstract: The present disclosure provides a manufacturing method of a package device, which includes providing a carrier substrate, a first conductive layer, and a release layer, where the carrier substrate has a device region and a peripheral region, and the first conductive layer and the release layer are disposed on the carrier substrate. The method further includes forming a second conductive layer on the release layer in the device region, where at least one of the first and second conductive layers includes a first pad in the peripheral region. The second conductive layer includes a second pad electrically connected to the first pad through the first conductive layer. The method also includes performing an inspection step to provide an input signal to one of the first and second pads, and to receive an output signal from another of the first and second pads.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: October 24, 2023
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Kuang-Chiang Huang, Yu-Ting Liu, Yi-Hung Lin, Cheng-En Cheng
  • Publication number: 20230326746
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer.
    Type: Application
    Filed: May 31, 2023
    Publication date: October 12, 2023
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Patent number: 11776914
    Abstract: A package device is provided and includes a redistribution layer. The redistribution layer includes a first dielectric layer, a second dielectric layer, and a conductive layer. The second dielectric layer is disposed on the first dielectric layer, and the second dielectric layer includes a dielectric pattern. The conductive layer is disposed between the first dielectric layer and the second dielectric layer, and the conductive layer includes a first conductive pattern. The dielectric pattern has a through hole, and in a top view of the package device, the first conductive pattern and the through hole are overlapped with each other.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: October 3, 2023
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Cheng-En Cheng, Yu-Ting Liu
  • Patent number: 11769685
    Abstract: A manufacturing method of a semiconductor package is provided. The manufacturing method includes the following. A plurality of semiconductor components are provided. Each semiconductor component has at least one conductive bump. A substrate is provided. The substrate has a plurality of conductive pads. A transfer device is provided. The transfer device transfers the semiconductor components onto the substrate. A heating device is provided. The heating device heats or pressurizes at least two semiconductor components. During transferring of the semiconductor components to the substrate, the at least one conductive bump of each semiconductor component is docked to a corresponding one of the conductive pads.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: September 26, 2023
    Assignee: Innolux Corporation
    Inventors: Cheng-Chi Wang, Wen-Hsiang Liao, Yeong-E Chen, Hung-Sheng Chou, Cheng-En Cheng