Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.

Abstract: A semiconductor process for forming gates with different pitches includes the following steps. A gate layer is formed on a substrate. A first mandrel and a second mandrel are respectively formed on the gate layer. A first spacer material is formed to conformally cover the first mandrel but exposing the second mandrel. A second spacer material is formed to conformally cover the first spacer material and the second mandrel. The first spacer material and the second spacer material are etched to form a first spacer beside the first mandrel and a second spacer beside the second mandrel simultaneously. The first mandrel and the second mandrel are removed. Layouts of the first spacer and the second spacer are transferred to the gate layer, thereby a first gate and a second gate being formed. Moreover, a semiconductor process, which forms the first spacer and the second spacer separately, is also provided.

Abstract: The present invention provides a semiconductor structure, including a substrate, a first nanowire structure disposed on the substrate, and the first nanowire structure includes a gate region and a source/drain region The diameter of the first nanowire structure within the gate region is different from the diameter of the first nanowire structure within the source/drain region.

Abstract: An overlay measurement method includes providing three predetermined patterns, including a first predetermined pattern, a second predetermined pattern and a third predetermined pattern. An inspection process is then performed on said three predetermined patterns, to obtain three image points, including a first image point, a second image point and a third image point respectively. Next, a defining process is performed to define a default position, and a calculating process is performed to obtain a real offset value x=(p?q)*(c?a)/(a?b)+p.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.

Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Abstract: A manufacturing method of a conductive structure in a semiconductor device includes the following steps. A plurality of gate structures are formed on a semiconductor structure, and a first dielectric layer is formed in space between the gate structures. A first process is then performed to remove at least a part of the first dielectric layer in the space between the gate structures. A second dielectric layer is then formed and covers the gate structures so as to form at least one air void in the space between the gate structures. A second process is performed to form at least one opening penetrating the second dielectric layer and exposing the air void. The air void exposed by the opening is then filled with at least one conductive material for forming a conductive structure between the gate structures.

Abstract: The present invention provides a semiconductor structure, including a substrate, a shallow trench isolation (STI) disposed in the substrate, a plurality of first fin structures disposed in the substrate, where each first fin structure and the substrate have same material, and a plurality of second fin structures disposed in the STI, where each second fin structure and the STI have same material.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a plurality of fin shaped structures and a dummy gate structure. The fin shaped structures are disposed in a substrate, where at least one of the fin shaped structures has a tipped end. The dummy gate structure is disposed on the substrate, and includes an extending portion covering the tipped end.

Abstract: A semiconductor device includes: a substrate, a fin-shaped structure on the substrate, and a dummy fin-shaped structure on the substrate and adjacent to the fin-shaped structure. Preferably, the fin-shaped structure includes a gate structure thereon and a first epitaxial layer adjacent to two sides of the gate structure, and the dummy fin-shaped structure includes a second epitaxial layer thereon. A contact plug is disposed on the first epitaxial layer and the second epitaxial layer.

Abstract: The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of mandrels on the first region and a plurality of patterns on the second region, in which the widths of the patterns on the second region are greater than the widths of the mandrels on the first region; forming a hard mask on the second region to cover the patterns; and forming a cap layer on the first region and the second region to cover the mandrels and the hard mask.

Abstract: In this disclosure, a mark segmentation method and a method for manufacturing a semiconductor structure applying the same are provided. The mark segmentation method comprises the following steps. First, a plurality of segments having a width WS and separated from each other by a space SS formed on a substrate are identified by a processor. Thereafter, a plurality of marks are set over the segments by the processor. This step comprises: (1) adjusting a width WM of each one of the marks being equal to m(WS+SS)+WS or m(WS+SS)+SS by the processor, wherein m is an integer; and (2) adjusting a space SM of adjacent two of the marks by the processor such that WM+SM=n(WS+SS), wherein n is an integer.

Abstract: An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a hard mask on the gate structure and the ILD layer; forming a first patterned mask layer on the hard mask; using the first patterned mask layer to remove part of the hard mask for forming a patterned hard mask; and utilizing a gas to strip the first patterned mask layer while forming a protective layer on the patterned hard mask, wherein the gas is selected from the group consisting of N2 and O2.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a sacrificial mandrel on the substrate, wherein the sacrificial mandrel comprises an indentation; and forming a spacer adjacent to the sacrificial mandrel.

Abstract: A method of forming a line pattern including following steps. First of all, a substrate having a first region and a second region is provided. Next, a directed self-assembly (DSA) material layer is formed on the substrate, covering the first region and the second region. Then, the DSA material layer in the second region is removed, to form a patterned DSA material layer. After these, an annealing process is performed to enable only the DSA material layer in the first region and to form a plurality of first stripe structures and a plurality of second stripe structures arranged alternately in a first direction.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract: The semiconductor structure includes a plurality of first insulators in a substrate, a common insulating layer surrounding the sidewall and the bottom of said first insulators in said substrate, and suspended portions of said substrate on said common insulating layer.

Abstract: The present invention provides a measurement mark structure, including a plurality of inner patterns, the inner patterns being arranged along a first direction, and an outer pattern, positioned surrounding the inner patterns, and the outer pattern is rectangular frame shaped.