Patents by Inventor En-Hsing Chen
En-Hsing Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120049186Abstract: Test structures are formed during semiconductor processing with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.Type: ApplicationFiled: August 31, 2010Publication date: March 1, 2012Inventors: Calvin K. Li, Yung-Tin Chen, En-Hsing Chen, Paul Wai Kie Poon
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Patent number: 7998640Abstract: A mask is reused to form the same pattern in multiple layers in semiconductor processing. Reference marks that allow alignment accuracy to be checked are also formed with the mask. The manner of using the mask advantageously mitigates interference between reference marks in different layers.Type: GrantFiled: June 30, 2007Date of Patent: August 16, 2011Assignee: SanDisk CorporationInventors: Calvin K. Li, Yung-Tin Chen, En-Hsing Chen, Paul Wai Kie Poon
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Patent number: 7932157Abstract: Test structures are formed during semiconductor processing. The test structures allow performance characteristics to be monitored as the process proceeds. The test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent levels are patterned. The manner of using the mask also allows different types of test structures having different features to be formed. The different types of test structures can provide insight into performance characteristics of different types of devices.Type: GrantFiled: June 30, 2007Date of Patent: April 26, 2011Assignee: SanDisk CorporationInventors: Calvin K. Li, Yung-Tin Chen, En-Hsing Chen, Paul Wai Kie Poon
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Patent number: 7830028Abstract: Different types of test structures are formed during semiconductor processing. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.Type: GrantFiled: June 30, 2007Date of Patent: November 9, 2010Assignee: SanDisk CorporationInventors: Calvin K. Li, Yung-Tin Chen, En-Hsing Chen, Paul Wai Kie Poon
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Patent number: 7508714Abstract: An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.Type: GrantFiled: May 21, 2007Date of Patent: March 24, 2009Assignee: SanDisk 3D LLCInventors: Luca G. Fasoli, Roy E. Scheuerlein, En-Hsing Chen, Sucheta Nallamothu, Maitreyee Mahajani, Andrew J. Walker
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Patent number: 7505321Abstract: A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer.Type: GrantFiled: December 31, 2002Date of Patent: March 17, 2009Assignee: SanDisk 3D LLCInventors: Roy E. Scheuerlein, Christopher Petti, Andrew J. Walker, En-Hsing Chen, Sucheta Nallamothu, Alper Ilkbahar, Luca Fasoli, Igor Koutnetsov
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Publication number: 20090004880Abstract: A mask is reused to form the same pattern in multiple layers in semiconductor processing. Reference marks that allow alignment accuracy to be checked are also formed with the mask. The manner of using the mask advantageously mitigates interference between reference marks in different layers.Type: ApplicationFiled: June 30, 2007Publication date: January 1, 2009Inventors: Calvin K. Li, Yung-Tin Chen, En-Hsing Chen, Paul Wai Kie Poon
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Publication number: 20090004879Abstract: Test structures are formed during semiconductor processing. The test structures allow performance characteristics to be monitored as the process proceeds. The test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent levels are patterned. The manner of using the mask also allows different types of test structures having different features to be formed. The different types of test structures can provide insight into performance characteristics of different types of devices.Type: ApplicationFiled: June 30, 2007Publication date: January 1, 2009Inventors: Calvin K. Li, Yung-Tin Chen, En-Hsing Chen, Paul Wai Kie Poon
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Publication number: 20090001615Abstract: Different types of test structures are formed during semiconductor processing. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.Type: ApplicationFiled: June 30, 2007Publication date: January 1, 2009Inventors: Calvin K. Li, Yung-Tin Chen, En-Hsing Chen, Paul Wai Kie Poon
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Patent number: 7433233Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.Type: GrantFiled: June 18, 2007Date of Patent: October 7, 2008Assignee: SanDisk 3D LLCInventors: En-Hsing Chen, Andrew J. Walker, Roy E. Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca G. Fasoli
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Publication number: 20070242511Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.Type: ApplicationFiled: June 18, 2007Publication date: October 18, 2007Inventors: En-Hsing Chen, Andrew Walker, Roy Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca Fasoli
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Publication number: 20070217263Abstract: An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.Type: ApplicationFiled: May 21, 2007Publication date: September 20, 2007Inventors: Luca Fasoli, Roy Scheuerlein, En-Hsing Chen, Sucheta Nallamothu, Maitreyee Mahajani, Andrew Walker
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Patent number: 7233522Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.Type: GrantFiled: December 5, 2003Date of Patent: June 19, 2007Assignee: SanDisk 3D LLCInventors: En-Hsing Chen, Andrew J. Walker, Roy E. Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca G. Fasoli
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Patent number: 7221588Abstract: An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, and NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.Type: GrantFiled: December 5, 2003Date of Patent: May 22, 2007Assignee: Sandisk 3D LLCInventors: Luca G. Fasoli, Roy E. Scheuerlein, En-Hsing Chen, Sucheta Nallamothu, Maitreyee Mahajani, Andrew J. Walker
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Patent number: 7023739Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.Type: GrantFiled: December 5, 2003Date of Patent: April 4, 2006Assignee: Matrix Semiconductor, Inc.Inventors: En-Hsing Chen, Andrew J. Walker, Roy E. Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca G. Fasoli
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Publication number: 20060067127Abstract: A method of programming a monolithic three-dimensional (3-D) memory having a plurality of levels of memory cells above a silicon substrate is disclosed. The method includes initializing a program voltage and program time interval; selecting a memory cell to be programmed within the three-dimensional memory having the plurality of levels of memory cells; applying a pulse having the program voltage and the program time interval to the selected memory cell; performing a read after write operation with respect to the selected memory cell to determine a measured threshold voltage value; and comparing the measured threshold voltage value to a minimum program voltage. In response to the comparison between the measured threshold voltage value and the minimum program voltage, the method further includes selectively applying at least one subsequent program pulse to the selected memory cell.Type: ApplicationFiled: September 30, 2004Publication date: March 30, 2006Inventors: Luca Fasoli, Roy Scheuerlein, Alper Ilkbahar, En-Hsing Chen, Tanmay Kumar
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Patent number: 7012299Abstract: The traditional nitride-only charge storage layer of a SONOS device is replaced by a multifilm charge storage layer comprising more than one dielectric material. Examples of such a multifilm charge storage layer are alternating layers of silicon nitride and silicon dioxide, or alternating layers of silicon nitride and aluminum oxide. The use of more than one material introduces additional barriers to migration of charge carriers within the charge storage layer, and improves both endurance and retention of a SONOS-type memory cell comprising such a charge storage layer.Type: GrantFiled: September 23, 2003Date of Patent: March 14, 2006Assignee: Matrix Semiconductors, Inc.Inventors: Maitreyee Mahajani, Andrew J. Walker, En-Hsing Chen
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Patent number: 7005350Abstract: A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer.Type: GrantFiled: December 31, 2002Date of Patent: February 28, 2006Assignee: Matrix Semiconductor, Inc.Inventors: Andrew J. Walker, En-Hsing Chen, Sucheta Nallamothu, Roy E. Scheuerlein, Alper Ilkbahar, Luca Fasoli, Igor Koutnetsov, Christopher Petti
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Patent number: 6960794Abstract: A thin film transistor with a channel less than 100 angstroms thick, preferably less than 80 angstroms thick, preferably less than 60 angstroms thick. The very thin channel reduces variability of threshold voltage from one TFT to the next. This is particularly advantageous for TFT memory arrays. It is possible that an extremely thin channel restricts the size of grains, forcing many small grains to be formed.Type: GrantFiled: December 31, 2002Date of Patent: November 1, 2005Assignee: Matrix Semiconductor, Inc.Inventors: Andrew J. Walker, S. Brad Herner, Maitreyee Mahajani, En-Hsing Chen, Roy E. Scheuerlein, Sucheta Nallamothu, Mark Clark
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Publication number: 20050128807Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.Type: ApplicationFiled: December 5, 2003Publication date: June 16, 2005Inventors: En-Hsing Chen, Andrew Walker, Roy Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca Fasoli, James Cleeves