Abstract: A time offset measurement method suitable for Non-Terrestrial Network includes: listening to the first downlink signal and the second downlink signal through the user device to obtain the first reception time and the second reception time; using the known interval time as the unit time length to calculate multiple satellite distance difference values corresponding to multiple unit time lengths through a satellite distance function, obtaining multiple satellite movement time variations through dividing multiple satellite distance difference values by the electromagnetic wave propagation speed, generating a satellite movement function based on each sampling time and each of the satellite movement time variations corresponding to each sampling time; setting the reception time difference to calculate the corresponding sampling time through the satellite movement function as the downlink signal reception time; and obtaining the current distance between the user device and the satellite at the second reception time

Abstract: A two-stage system and method for treating fluoride-containing wastewater are provided. The two-stage system includes a first concentration defluoridation section and a second concentration defluoridation section. In the first concentration defluoridation section, the first mixed wastewater containing high concentration of fluoride ions is mixed with calcium chloride and stirred in the second mixing tank to obtain the second mixed wastewater containing low-concentration fluoride ions; in the second concentration defluoridation section, the second mixed wastewater is mixed with an advanced defluoridation agent and stirred in the third mixing tank to form a third mixed wastewater; the third mixed wastewater is introduced into a flocculation tank from the third mixing tank; and polymer is added for flocculation and sedimentation, so as to discharge a sediment and a defluoridation wastewater, the fluoride ion of which is less than 15 ppm.

Abstract: An advanced defluoridation agent and a method for removing fluoride ions in fluorine-containing wastewater are provided. The advanced defluoridation agent includes 40-70 wt % of polyaluminum sulfate, 0.3-30 wt % of hydroxyapatite and deionized water supplemented to 100 wt %. Using the advanced defluoridation agent of the present disclosure to treat fluoride-containing wastewater can achieve increased defluorination efficiency, reduced electrical conductivity, and reduced sludge content, and a better defluorination effect. The concentration of fluoride ions is lower than 15 ppm after using the advanced defluoridation agent of the present disclosure.

Abstract: Distributed orchestration of data retrieval for generative machine learning model may be performed. When a natural language request to perform a natural language task is received that is associated with a generative application, one or more data retrievers may be selected to access associated data repositories according to a previously specified retrieval configuration for the generative natural language application. The data may then be obtained by the selected data retrievers and used to generate a prompt to a generative machine learning model. A result of the generative machine learning model may then be used to provide a response to the natural language request to perform the natural language task.

Abstract: Various embodiments include protection layers for a transistor and methods of forming the same. In an embodiment, a method includes: exposing a semiconductor nanostructure, a dummy nanostructure, and an isolation region by removing a dummy gate; increasing a deposition selectivity between a top surface of the semiconductor nanostructure and a top surface of the isolation region relative a selective deposition process; depositing a protection layer on the top surface of the isolation region by performing the selective deposition process; removing the dummy nanostructure by selectively etching a dummy material of the dummy nanostructure at a faster rate than a protection material of the protection layer; and forming a gate structure around the semiconductor nanostructure.

Abstract: Systems, methods, and other embodiments described herein relate to generating designs using learning models for analogics that process text and sketch-based inputs. In one embodiment, a method includes estimating analogical suggestions using a transformer model for a text prompt having design parameters. The method also includes generating an image using a learning model for an expression selected from the analogical suggestions and a sketched stroke inputted. The method also includes manipulating a modified sketch by the learning model and the modified sketch is derived from a sketched conversion of the image by an edge model.

Abstract: A method includes depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming first spacers on the first mandrel and second spacers on the second mandrel; and selectively removing the second spacers while masking the first spacers. Masking the first spacers comprising covering the first spacers with a second mask and a capping layer over the second mask, and the capping layer comprises carbon. The method further includes patterning the first mask and transferring a pattern of the first mask to the target layer. Patterning the first mask comprises masking the first mask with the second mandrel, the first mandrel, and the first spacers.

Abstract: In an embodiment, a method includes: forming a photoresist over a target layer; performing a plasma-enhanced deposition process, the plasma-enhanced deposition process etching sidewalls of the photoresist while depositing a spacer layer on the sidewalls of the photoresist; patterning the spacer layer to form spacers on the sidewalls of the photoresist; and etching the target layer using the spacers and the photoresist as a combined etching mask.

Abstract: Systems, methods, and other embodiments described herein relate to identifying and generating mechanisms from natural processes by a learning model for accelerating design development. In one embodiment, a method includes identifying mechanisms for a design task using a prompt transformer with seeds from biological processes, and the prompt transformer forms a taxonomy tree using the mechanisms. The method also includes generating functional solutions that expand sparse branches of the taxonomy tree for the mechanisms using the prompt transformer. The method also includes clustering the mechanisms using text embedding for the design task. The method also includes inspecting the mechanisms with the prompt transformer to select a solution associated with the design task.

Abstract: A method for filling a gap includes: filling a dielectric layer in the gap so that a seam is formed in the dielectric layer, the dielectric layer including two surface portions at two opposite sides of the seam, respectively; introducing a surface modification agent into the seam such that each of the two surface portions has first functional groups and second functional groups; forming a stress layer on the dielectric layer to cover the seam, the stress layer including a material different from that of the dielectric layer; and applying an energy field to permit the two surface portions to bond with each other through reaction between the first functional groups and the second functional groups.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed over a substrate and between two adjacent semiconductor layers, an inner spacer disposed between and in contact with one semiconductor layer and the substrate, and a dielectric layer structure disposed between the S/D feature and the substrate. The dielectric layer structure includes a first dielectric layer in contact with the inner spacer and the substrate, and a second dielectric layer nested within the first dielectric layer, wherein a bottom surface and sidewall surfaces of the second dielectric layer are in contact with the first dielectric layer.

Abstract: Embodiments with present disclosure provides a gate-all-around FET device including extended bottom inner spacers. The extended bottom inner prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.

Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed in a recess between two adjacent channel regions, wherein the S/D feature comprises an epitaxial layer conformally deposited on an exposed surface of the recess. The structure also includes a silicide layer conformally disposed on the S/D feature, and a S/D contact disposed on the silicide layer, wherein the S/D contact has a first portion extending into the recess, and the first portion has at least three surfaces being surrounded by the silicide layer and the S/D feature.

Abstract: Provided is an uplink signal time difference adjustment method, adapted to a base station and including the following steps. Each first delay time of arrival of each uplink signal is detected based on a time slot boundary. Each second delay time of each uplink signal is adjusted according to multiple sampling points. Each time offset between each first delay time and each second delay time corresponding to each user apparatus is calculated. The time slot boundary is adjusted according to each time offset.

Abstract: The present disclosure belongs to the technical field of tools for bridge reinforcement, and particularly relates to a precisely-positioned drilling apparatus for steel tubular joints. According to the present disclosure, a lifting frame unit, an electric drill, a lever unit, a positioning tube unit, and a diagonal tensioning member unit are arranged on a base unit such that 1. during drilling, a drill rod is not prone to deviation, and a drilling action is relatively precise, resulting in an approximately circular shape of a final drilled hole; and 2. the above lever unit is essentially a labor-saving lever that ensures relatively easy and convenient drilling operations. Additionally, the present disclosure further discloses an application method of the apparatus, which ensures that the apparatus may stably fit with and be safely available for electric drills with various sizes and specifications.

Abstract: A computer peripheral device is provided. The computer peripheral device is adapted to be installed in an electronic device supporting signal transmission of a first signal frequency. The computer peripheral device includes a human interface device (HID) and a bridging device. The HID includes a control unit to support signal transmission of a second signal frequency. The bridging device includes a first universal serial bus (USB) interface unit and a second USB interface unit. The first USB interface unit is adapted to be electrically connected to the electronic device, and supports signal transmission of the first signal frequency. The second USB interface unit is adapted to be electrically connected to the HID. The second USB interface unit regards the HID as a communication device class (CDC) device, instructs the control unit to generate an input signal at a timing corresponding to the first signal frequency, and transmits the input signal to the electronic device.

Abstract: A method includes etching a semiconductor region aside of a gate stack to form a recess, forming a dielectric layer at a bottom of the recess, selectively forming a first semiconductor layer at the bottom of the recess, and epitaxially growing a second semiconductor layer on the first semiconductor layer. A bottom surface of the first semiconductor layer forms an interface with a top surface of the dielectric layer, with the interface extending to opposing sides of the recess. The selectively forming the first semiconductor layer comprises a first deposition process performed under first process conditions. The second semiconductor layer is formed using a second deposition process under second process conditions. The second process conditions are different from the first process conditions.

Abstract: A semiconductor device includes: a substrate; a fin protruding above the substrate; a gate structure over the fin; source/drain regions over the fin and on opposing sides of the gate structure; channel layers over the fin and between the source/drain regions, where the gate structure wraps around the channel layers; and isolation structures under the source/drain regions, where the isolation structures separate the source/drain regions from the fin, where each of the isolation structures includes a liner layer and a dielectric layer over the liner layer, where the dielectric layer has a plurality of sublayers.

Abstract: The present invention is related to water-borne polymers polymerized by radical polymerization with azo initiators, a process for making the polymers and the application thereof. The polymers polymerized with azo initiators show superior water-whitening resistance and scrub resistance, which are desired properties for coatings applications.