Patents by Inventor EN LIU

EN LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984668
    Abstract: A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Monsen Liu, Lai Wei Chih, Chung-Hao Tsai, Jeng-Shien Hsieh, En-Hsiang Yeh, Chuei-Tang Wang
  • Patent number: 11967959
    Abstract: The present invention discloses a clock data recovery method having quick locking and bandwidth stabilizing mechanism used in a clock data recovery circuit. A relative position relation between a serial data and a sampling clock is detected by a phase detection circuit in an adaptive control period to generate a tracking direction. The tracking direction of a first clock period is directly outputted as an adaptive tracking direction by an adaptive tracking circuit. For each of the clock periods behind the first clock period, a previous tracking direction is replaced by a current tracking direction only when the current tracking direction exists and is different from the previous tracking direction of a previous clock period such that an actual tracking direction is generated when the adaptive tracking direction changes. The phase of the sampling clock is adjusted according to the actual tracking direction by a clock control circuit.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: April 23, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Hsi-En Liu
  • Patent number: 11967272
    Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: April 23, 2024
    Assignees: AUO Corporation, National Cheng-Kung University
    Inventors: Chih-Lung Lin, Yi-Chen Huang, Chih-I Liu, Po-Cheng Lai, Ming-Yang Deng, Chia-En Wu, Ming-Hung Chuang, Chia-Tien Peng
  • Patent number: 11964149
    Abstract: A facial beautifying and care apparatus includes a beauty bar (1) having an air supply passage (A), a negative pressure connecting hole (132), a conductive suction nozzle (15) and a first connection port (134); an EMS generation module (20) inside the beauty bar (1) electrically connected to the first connection port (134); an external negative pressure unit (6) separated from the beauty bar (1) and having a negative pressure driving control module (62) and a second connection port (637); the negative pressure driving control module (62) having an air supply tube assembly (66) with a negative pressure communicating hole (661); a communicating tube (7) communicating with the negative pressure connecting hole (132) and the negative pressure communicating hole (661); a conductive wire (8) connected to the first connecting port (134) and the second connecting port (637). Accordingly, the effects of facial skin firming, cleaning, beautifying and caring are achieved.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: April 23, 2024
    Assignees: BIBOTING INTERNATIONAL CO., LTD.
    Inventors: Po-Chang Liu, Pei-En Lee
  • Patent number: 11962426
    Abstract: An Ethernet power supply receives a DC voltage through a bus positive terminal and a bus negative terminal, and is coupled to a load device. The Ethernet power supply includes a first control module and a second control module. The first control module is used to provide a first control signal through the bus negative terminal to confirm whether the load device is a valid load. The second control module is used to connect or disconnect a coupling relationship between the bus positive terminal and the first control module according to the load device being connected or not.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: April 16, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yung-Wei Peng, Kuan-Hsien Tu, Cheng-En Liu
  • Patent number: 11961852
    Abstract: Disclosed is a manufacture method of the array substrate, including: sequentially forming a gate, a gate insulating layer, an active layer, an ohmic contact layer and a metal layer on a substrate, forming a photoetching mask on the metal layer, where thickness of the photoetching mask in a half exposure area of the mask plate is from 2000 ? to 6000 ?; etching the metal layer, the ohmic contact layer and the active layer outside a covering area of the photoetching mask; ashing the photoetching mask for a preset time with an ashing reactant, wherein the ashing reactant comprises oxygen, and the preset time is from 70 seconds to 100 seconds; and sequentially etching the metal layer, the ohmic contact layer and the active layer based on the ashed photoetching mask, and forming a channel region of the array substrate. The present disclosure further discloses an array substrate, and a display panel.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: April 16, 2024
    Assignees: HKC CORPORATION LIMITED, CHUZHOU HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: En-Tsung Cho, Fengyun Yang, Yuming Xia, Je-Hao Hsu, Zhen Liu, Hejing Zhang, Wanfei Yong
  • Patent number: 11955201
    Abstract: A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yi-Ching Liu, Yih Wang
  • Patent number: 11953964
    Abstract: An Ethernet power supply receives a DC voltage through a bus positive terminal and a bus negative terminal, and is coupled to a load device. The Ethernet power supply includes a first control module and a second control module. The first control module provides a first control signal through the bus negative terminal to confirm whether the load device is a valid load. The second control module is used to connect or disconnect a coupling relationship between the bus positive terminal and the first control module according to whether the load device is connected to the Ethernet power supply.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: April 9, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yung-Wei Peng, Kuan-Hsien Tu, Cheng-En Liu
  • Patent number: 11947828
    Abstract: A memory device is disclosed, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: April 2, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Jun-Shen Wu, Chi-En Wang, Ren-Shuo Liu
  • Publication number: 20240102950
    Abstract: A method for determining parameters of nanostructures, wherein the method includes steps as follows: Firstly, an X-ray reflection intensity measurement curve of a nanostructure to be tested is obtained by radiating the nanostructure to be tested with X-ray. The X-ray reflection intensity measurement curve is compared with an X-ray reflection intensity standard curve to obtain a comparison result. Subsequently, at least one parameter existing in the nanostructure to be tested is determined according to the comparison result.
    Type: Application
    Filed: September 28, 2023
    Publication date: March 28, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Ting LIU, Po-Ching HE, Wei-En FU, Chun-Yu LIU
  • Patent number: 11942177
    Abstract: One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Ta Yu, Chia-En Huang, Sai-Hooi Yeong, Yih Wang, Yi-Ching Liu
  • Patent number: 11943355
    Abstract: Methods and compositions for decentralized systems for mitigating climate change are provided. In some embodiments, the compositions comprise: one or more first servers operable to store a plurality of first tokens, wherein each one of the plurality of first tokens is associated with fiscal value; one or more second servers operable to store a plurality of second tokens, wherein each one of the plurality of second tokens corresponds to a unit of voting power; one or more project developer nodes operable to transmit project data corresponding to renewable energy or carbon sequestration; one or more auditor nodes operable to verify an identity, validate credentials, perform a project assessment, generate a smart contract, receive signals, and transmit signals; and one or more steward nodes, wherein each one of the one or more steward nodes is operable to stake tokens for voting power and to distribute voting power.
    Type: Grant
    Filed: August 3, 2022
    Date of Patent: March 26, 2024
    Assignee: Hunt Energy Enterprises, L.L.C.
    Inventors: Ross E. Freeman, Victor Kuang-en Liu, Mark H. Griffin, Robert D. Maher, III, John F. Allen, Jr.
  • Publication number: 20240096386
    Abstract: A memory circuit includes a first memory cell on a first layer, a second memory cell on a second layer different from the first layer, a first select transistor on a third layer different from the first layer and the second layer, and a first bit line extending in a first direction, and being coupled to the first memory cell and the second memory cell. The memory circuit further includes a first source line extending in the first direction, being coupled to the first memory cell, the second memory cell and the first select transistor, and being separated from the first bit line in a second direction different from the first direction. memory circuit includes a second source line extending in the first direction, and being coupled to the first select transistor.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Yi-Ching LIU, Chia-En HUANG, Yih WANG
  • Publication number: 20240095930
    Abstract: A machine learning method includes: distinguishing foregrounds and backgrounds of a first image to generate a first mask image; cropping the first image to generate second and third images; cropping the first mask image to generate second and third mask images, wherein a position of the second mask image and a position of the third mask image correspond to a position of the second image and a position of the third image, respectively; generating a first feature vector group of the second image and a second feature vector group of the third image by a model; generating a first matrix according to the first and second feature vector groups; generating a second matrix according to the second and third mask images; generating a function according to the first and second matrices; and adjusting the model according to the function.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 21, 2024
    Inventors: Shen-Hsuan LIU, Van Nhiem TRAN, Kai-Lin YANG, Chi-En HUANG, Muhammad Saqlain ASLAM, Yung-Hui LI
  • Publication number: 20240094148
    Abstract: This disclosure relates to an X-ray reflectometry apparatus and a method for measuring a three-dimensional nanostructure on a flat substrate. The X-ray reflectometry apparatus comprises an X-ray source, an X-ray reflector, a 2-dimensional X-ray detector, and a two-axis moving device. The X-ray source is for emitting X-ray. The X-ray reflector is configured for reflecting the X-ray onto a sample surface. The 2-dimensional X-ray detector is configured to collect a reflecting X-ray signal from the sample surface. The two-axis moving device is configured to control two-axis directions of the 2-dimensional X-ray detector to move on at least one of x-axis and z-axis with a formula concerning an incident angle of the X-ray with respect to the sample surface for collecting the reflecting X-ray signal.
    Type: Application
    Filed: November 28, 2022
    Publication date: March 21, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Bo-Ching HE, Chun-Ting LIU, Wei-En FU, Wen-Li WU
  • Publication number: 20240087947
    Abstract: A semiconductor device and method of manufacture are provided. In some embodiments isolation regions are formed by modifying a dielectric material of a dielectric layer such that a first portion of the dielectric layer is more readily removed by an etching process than a second portion of the dielectric layer. The modifying of the dielectric material facilitates subsequent processing steps that allow for the tuning of a profile of the isolation regions to a desired geometry based on the different material properties of the modified dielectric material.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 14, 2024
    Inventors: Chung-Ting Ko, Yu-Cheng Shiau, Li-Jung Kuo, Sung-En Lin, Kuo-Chin Liu
  • Publication number: 20240085715
    Abstract: A field-of-view stitching system including: a light source module for emitting a first beam; a light guiding element for splitting the first beam into a plurality of second beams and includes an incident surface, a first exit surface, and a plurality of second exit surfaces, the second beams propagate along an optical path of the first beam; and a plurality of light modulators, a number of the plurality of light modulators is the same as a total number of the first exit surface and the plurality of second exit surfaces, each of the plurality of light modulators is configured to receive and regularly reflect one of the plurality of second beams; the light guiding element is further configured to receive and combine the second beams reflected by the light modulators to form an illuminating light. A field-of-view stitching method, a biological sample identification device and method are also provided.
    Type: Application
    Filed: April 30, 2021
    Publication date: March 14, 2024
    Inventors: EN BO, LI-YAN SONG, ANG LIU, QING-SHAN LONG, SHENG-YUAN ZHOU
  • Patent number: 11923392
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Jen-Cheng Liu, Kazuaki Hashimoto, Ming-En Chen, Shyh-Fann Ting, Shuang-Ji Tsai, Wei-Chieh Chiang
  • Publication number: 20240048383
    Abstract: Methods and compositions for decentralized systems for mitigating climate change are provided. In some embodiments, the compositions comprise: one or more first servers operable to store a plurality of first tokens, wherein each one of the plurality of first tokens is associated with fiscal value; one or more second servers operable to store a plurality of second tokens, wherein each one of the plurality of second tokens corresponds to a unit of voting power; one or more project developer nodes operable to transmit project data corresponding to renewable energy or carbon sequestration; one or more auditor nodes operable to verify an identity, validate credentials, perform a project assessment, generate a smart contract, receive signals, and transmit signals; and one or more steward nodes, wherein each one of the one or more steward nodes is operable to stake tokens for voting power and to distribute voting power.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 8, 2024
    Inventors: Ross E. Freeman, Victor Kuang-en Liu, Mark H. Griffin, Robert D. Maher, III, John F. Allen, JR.
  • Patent number: 11893923
    Abstract: A display apparatus is provided, which includes a display module, a biosensor, an ambient-light sensor, and a display controller. The ambient-light sensor is configured to detect ambient-light brightness and an ambient-light color temperature of the display apparatus. The display controller is configured to receive a video signal from a host, and displays the video signal on the display module. When the biosensor detects that a user is located in front of the display apparatus, the biosensor transmits an image-adjustment control signal to the display controller to control the display apparatus to enter an image-adjustment mode. When the display apparatus is in the image-adjustment mode, the display controller adjusts screen brightness and a screen color temperature of the image signal displayed on the display module according to the ambient-light brightness and the ambient-light color temperature.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: February 6, 2024
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Cheng-Lung Lin, Chih-Cheng Huang, Tzu-Yi Tsao, Chia-En Liu