Abstract: An integrated circuit structure comprises a base and a plurality of metal levels over the base. A first metal level includes a first dielectric material. The first metal level further includes a first plurality of interconnect lines in the first dielectric material, wherein the first plurality of interconnect lines in the first metal level have variable widths from relatively narrow to relatively wide, and wherein the first plurality of interconnect lines have variable heights based on the variable widths, such that a relatively wide one of the first plurality of interconnect lines has a taller height from the substrate than a relatively narrow one of the first plurality of interconnect lines, and a shorter distance to a top of the first metal level.

Abstract: The present invention provides an automatic deviation correction control method for a hoisting system, comprising the following steps: obtaining a lateral displacement X and an advancing included angle ? generated by the deflection of the hoisting system; when the lateral displacement X is not 0 and the advancing included angle ? is not 0, determining whether the lateral displacement X and the advancing included angle ? satisfy a preset condition; if the lateral displacement X and the advancing included angle ? do not satisfy the preset condition, controlling the hoisting system to correct the deviation toward a center line; and if the lateral displacement X and the advancing included angle ? satisfy the preset condition, controlling the hoisting system to correct the deviation toward the center line in a reverse direction.

Abstract: The present invention provides an automatic container landing device based on an expert system and a control method therefor.

Abstract: The present invention provides an automatic container landing device based on an expert system and a control method therefor.

Abstract: The present invention provides an automatic deviation correction control method for a hoisting system, comprising the following steps: obtaining a lateral displacement X and an advancing included angle ? generated by the deflection of the hoisting system; when the lateral displacement X is not 0 and the advancing included angle ? is not 0, determining whether the lateral displacement X and the advancing included angle ? satisfy a preset condition; if the lateral displacement X and the advancing included angle ? do not satisfy the preset condition, controlling the hoisting system to correct the deviation toward a center line; and if the lateral displacement X and the advancing included angle ? satisfy the preset condition, controlling the hoisting system to correct the deviation toward the center line in a reverse direction.

Abstract: An image recognition method, including: obtaining an image to be recognized by an image sensor; inputting the image to be recognized to a single convolutional neural network; obtaining a first feature map of a first detection task and a second feature map of a second detection task according to an output result of the single convolutional neural network, wherein the first feature map and the second feature map have a shared feature; using an end-layer network module to generate a first recognition result corresponding to the first detection task from the image to be recognized according to the first feature map, and to generate a second recognition result corresponding to the second detection task from the image to be recognized according to the second feature map; and outputting the first recognition result corresponding to the first detection task and the second recognition result corresponding to the second detection task.

Abstract: An image recognition method, including: obtaining an image to be recognized by an image sensor; inputting the image to be recognized to a single convolutional neural network; obtaining a first feature map of a first detection task and a second feature map of a second detection task according to an output result of the single convolutional neural network, wherein the first feature map and the second feature map have a shared feature; using an end-layer network module to generate a first recognition result corresponding to the first detection task from the image to be recognized according to the first feature map, and to generate a second recognition result corresponding to the second detection task from the image to be recognized according to the second feature map; and outputting the first recognition result corresponding to the first detection task and the second recognition result corresponding to the second detection task.

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ?-shape, L-shape, or ?-shape, for example.

Abstract: An integrated circuit structure comprises a base and a plurality of metal levels over the base. A first metal level includes a first dielectric material. The first metal level further includes a first plurality of interconnect lines in the first dielectric material, wherein the first plurality of interconnect lines in the first metal level have variable widths from relatively narrow to relatively wide, and wherein the first plurality of interconnect lines have variable heights based on the variable widths, such that a relatively wide one of the first plurality of interconnect lines has a taller height from the substrate than a relatively narrow one of the first plurality of interconnect lines, and a shorter distance to a top of the first metal level.

Abstract: Techniques are disclosed for forming a transistor with one or more additional gate spacers. The additional spacers may be formed between the gate and original gate spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion and an upper portion. In some such cases, the lower portion of the gate may be narrower in width between the original gate spacers than the upper portion of the gate, which may be as a result of the additional spacers being located between the lower portion of the gate and the original gate spacers. In some such cases, the gate may approximate a “T” shape or various derivatives of that shape such as -shape or -shape, for example.

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ?-shape, L-shape, or ?-shape, for example.

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ?-shape, L-shape, or ?-shape, for example.

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

Abstract: A method for integrating a many-core processor system with a network router comprises a subnet division step used for dividing an on-chip network into network requests in multiple subnet balance chips, and a network interface device deployment step used for deploying at least one network interface device in a subnet in a distributed mode in order to guarantee optimization of the connectivity between the deployed network interface device and the processor cores in the subnets and to implement rapid data exchange of the on-chip network or the inter-chip network. A many-core processor system integrated with a network router comprises a network router used for network interfacing and data exchange, and comprising multiple network interface devices embedded into the on-chip network in a distributed mode.

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

Abstract: Techniques are disclosed for forming a transistor with one or more additional gate spacers. The additional spacers may be formed between the gate and original gate spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion and an upper portion. In some such cases, the lower portion of the gate may be narrower in width between the original gate spacers than the upper portion of the gate, which may be as a result of the additional spacers being located between the lower portion of the gate and the original gate spacers. In some such cases, the gate may approximate a “T” shape or various derivatives of that shape such as -shape or -shape, for example.

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ?-shape, L-shape, or J-shape, for example.

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

Abstract: The present invention discloses a method for integrating a many-core processor system with a network router. The method comprises a subnet division step used for dividing an on-chip network into network requests in multiple subnet balance chips, and a network interface device deployment step used for deploying at least one network interface device in a subnet in a distributed mode in order to guarantee optimization of the connectivity between the deployed network interface device and the processor cores in the subnets and to implement rapid data exchange of the on-chip network or the inter-chip network. The present invention also discloses a many-core processor system integrated with a network router. The system comprises a network router used for network interfacing and data exchange, and comprising multiple network interface devices embedded into the on-chip network in a distributed mode.