Patents by Inventor Ende Shan

Ende Shan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6906421
    Abstract: This invention relates to a method of forming a local interconnect and a semiconductor device comprising a local interconnect. The semiconductor device comprises: a) a dielectric outside layer; and b) a conductivity structure comprising: i) at least one barrier layer having a thickness of 10-200 ? on a surface of said oxide layer; and ii) a conductive layer comprising titanium, on said at least one barrier layer, said at least one barrier layer preventing diffusion of oxygen from said dielectric oxide layer into said conductive layer and having a corresponding oxide that is not soluble in said conductive layer.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: June 14, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ende Shan, Gorley Lau, Anthony Chung
  • Patent number: 6756302
    Abstract: The invention concerns a method of forming a layer of metal on a substrate and fill the via with high throughput. A layer of metal can be formed on a substrate using sequentially a cold deposition step, a slow hot deposition step and a rapid hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit a seed layer of metal over the entire surface on which the metal layer is to be formed. In the slow hot deposition step, further metal is deposited at a power allowing for surface diffusion of the deposited metal, which is then followed by a rapid hot deposition of metal under bulk diffusion conditions.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: June 29, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ende Shan, Gorley Lau, Sam Geha
  • Patent number: 6746950
    Abstract: A low temperature aluminum planarization process. Vias, including high aspect ratio vias, are filled using a liner layer, a seed layer, and a fill layer. The device associated with the via is exposed to a reactive gas prior to applying the fill layer to the device.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: June 8, 2004
    Assignee: Vitesse Semiconductor Corporation
    Inventor: Ende Shan
  • Publication number: 20030092255
    Abstract: A low temperature aluminum planarization process. Vias, including high aspect ratio vias, are filled using a liner layer, a seed layer, and a fill layer. The device associated with the via is exposed to a reactive gas prior to applying the fill layer to the device.
    Type: Application
    Filed: November 14, 2001
    Publication date: May 15, 2003
    Inventor: Ende Shan
  • Patent number: 6534398
    Abstract: A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing “bumps” or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: March 18, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: Ende Shan, Gorley Lau, Sam G. Geha
  • Publication number: 20010008793
    Abstract: A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing “bumps” or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.
    Type: Application
    Filed: January 12, 2001
    Publication date: July 19, 2001
    Applicant: Cypress Semiconductor Corp.
    Inventors: Ende Shan, Gorley Lau, Sam G. Geha
  • Patent number: 6187667
    Abstract: A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing “bumps” or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: February 13, 2001
    Assignee: Cypress Semiconductor Corp.
    Inventors: Ende Shan, Gorley Lau, Sam G. Geha
  • Patent number: 6156645
    Abstract: A wetting layer is formed on a substrate at a relatively high process temperature (e.g., the temperature of the substrate and/or the temperature within a process chamber in which the wetting layer is formed). A metallization layer that is subsequently formed on the wetting layer adheres to the wetting layer better than the metallization layer would adhere to the wetting layer if the wetting layer was formed at a lower process temperature. The high process temperature causes the density of the wetting layer to be increased, so that, consequently, the wetting layer has a smoother surface to which the metallization layer can adhere.
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: December 5, 2000
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sam G. Geha, Ende Shan
  • Patent number: 6140228
    Abstract: The invention concerns a method of forming a layer of metal on a substrate and fill the via with high throughput. A layer of metal can be formed on a substrate using sequentially a cold deposition step, a slow hot deposition step and a rapid hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit a seed layer of metal over the entire surface on which the metal layer is to be formed. In the slow hot deposition step, further metal is deposited at a low power allowing for surface diffusion of the deposited metal, which is then followed by a rapid hot deposition of metal under bulk diffusion conditions.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: October 31, 2000
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ende Shan, Gorley Lau, Sam Geha
  • Patent number: 5968851
    Abstract: The present invention relates to a method of manufacturing an opening through a dielectric layer. The method comprises treating a polished dielectric layer with a wet etch selectively enchancing composition, such as buffered HF, prior to the formation of a patterned photoresist to improve the lateral-to-vertical wet etch ratio.
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: October 19, 1999
    Assignee: Cypress Semiconductor Corp.
    Inventors: Sam Geha, Ende Shan