Abstract: According to an embodiment, a test system for serially testing of finite state machine circuits using scan chains is proposed. Each scan chain is coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto. Each scan chain has a number of input terminals and one output terminal. The test system includes a dispatcher input interface with a number of input terminals and multiple sets of output terminals, where each set of output terminals includes multiple output terminals coupled to the input terminals of an associated scan chain. The test system further includes a dispatcher output interface with multiple input terminals and one output terminal. The output terminal of each scan chain is coupled to one of the input terminals of the dispatcher output interface.

Abstract: An embodiment asynchronous finite state machine (AFSM) circuit includes a first state register configured to output a first state acknowledgment signal in response to the AFSM circuit transitioning to a first state, a second state register configured to output a second state acknowledgment signal in response to the AFSM circuit transitioning to a second state, a first acknowledgement branch configured to convey the second state acknowledgment signal from the second state register to the first state register, a second acknowledgement branch configured to convey the first state acknowledgment signal from the first state register to the second state register, and transition logic circuitry.

Abstract: An asynchronous finite state machine (FSM) circuit comprises an arc cell configured to receive an analog input signal candidate for propagation over the FSM circuit as an output signal from the arc cell. In response to glitch affecting the analog input signal to the arc cell propagation over the FSM circuit of the analog input signal affected by glitch is conditioned upon either one of: i) the glitch being suppressed at the output of the arc cell, or ii) the glitch being latched within the arc cell. Propagation over the FSM circuit of the analog input signal affected by glitch takes place in response to the glitch being suppressed at the output of the arc cell irrespective of the glitch being latched within the arc cell.

Abstract: According to an embodiment, a test system for serially testing of finite state machine circuits using scan chains is proposed. Each scan chain is coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto. Each scan chain has a number of input terminals and one output terminal. The test system includes a dispatcher input interface with a number of input terminals and multiple sets of output terminals, where each set of output terminals includes multiple output terminals coupled to the input terminals of an associated scan chain. The test system further includes a dispatcher output interface with multiple input terminals and one output terminal. The output terminal of each scan chain is coupled to one of the input terminals of the dispatcher output interface.

Abstract: According to an embodiment, an integrated circuit includes a complementary metal-oxide-semiconductor (CMOS) logic gate, a series p-channel transistor, and a shunt n-channel transistor. The CMOS logic gate includes a first p-channel transistor and a first n-channel transistor. The first p-channel transistor and the series p-channel transistor are configurable to be body biased. The series p-channel transistor is coupled between an output terminal of the CMOS logic gate and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal of the CMOS logic gate and the reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.

Abstract: According to an embodiment, an integrated circuit includes a complementary metal-oxide-semiconductor (CMOS) logic gate, a series p-channel transistor, and a shunt n-channel transistor. The CMOS logic gate includes a first p-channel transistor and a first n-channel transistor. The first p-channel transistor and the series p-channel transistor are configurable to be body biased. The series p-channel transistor is coupled between an output terminal of the CMOS logic gate and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal of the CMOS logic gate and the reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.

Abstract: A register bank includes a plurality of without-reset registers. The register bank has a write input, a write-enable input, and a write-address input coupled to the plurality of without-reset registers. The register bank has a plurality of operating modes, including an initialization mode of operation and a write mode of operation. In the initialization mode of operation, the register bank responds to receipt of a write-enable signal on the write-enable input by storing initialization data received on the write input into a register of the first plurality of without-reset registers based on a write-address signal received on the write-address input.

Abstract: A method to test an asynchronous finite state machine for faults, the method including disabling state transitions out of a state of the asynchronous finite state machine and inputting test data to the AFSM to trigger a transition from the state to an expected state. The method further including enabling transitions out of the state of the asynchronous finite state machine, and determining whether the asynchronous finite state machine has performed a successful transition to the expected state.

Abstract: A method to test an asynchronous finite state machine for faults, the method including disabling state transitions out of a state of the asynchronous finite state machine and inputting test data to the AFSM to trigger a transition from the state to an expected state. The method further including enabling transitions out of the state of the asynchronous finite state machine, and determining whether the asynchronous finite state machine has performed a successful transition to the expected state.