Patents by Inventor Eng Chye Chua

Eng Chye Chua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip package interaction (CPI) back-end-of-line (BEOL) monitoring structure and method
    Patent number: 10643912
    Abstract: Various embodiments include monitoring structures for integrated circuits (ICs) and related monitoring methods. In some cases, a monitoring structure includes: a set of serpentine-comb structures configured to connect with a back-end-of-line (BEOL) portion of the IC, each of the serpentine-comb structures including: a chain of interconnected laterally extending wires spanning a set of metal levels in the IC; and a set of vias connecting the chain of interconnected laterally extending wires across the set of metal levels, wherein the set of vias includes at least one via spanning between each successive level of the chain of interconnected laterally extending wires, wherein the chain of interconnected laterally extending wires and the set of vias are configured to detect a chip package interface (CPI) failure in the IC.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Scott K. Pozder, Eng Chye Chua
  • CHIP PACKAGE INTERACTION (CPI) BACK-END-OF-LINE (BEOL) MONITORING STRUCTURE AND METHOD
    Publication number: 20190027413
    Abstract: Various embodiments include monitoring structures for integrated circuits (ICs) and related monitoring methods. In some cases, a monitoring structure includes: a set of serpentine-comb structures configured to connect with a back-end-of-line (BEOL) portion of the IC, each of the serpentine-comb structures including: a chain of interconnected laterally extending wires spanning a set of metal levels in the IC; and a set of vias connecting the chain of interconnected laterally extending wires across the set of metal levels, wherein the set of vias includes at least one via spanning between each successive level of the chain of interconnected laterally extending wires, wherein the chain of interconnected laterally extending wires and the set of vias are configured to detect a chip package interface (CPI) failure in the IC.
    Type: Application
    Filed: July 24, 2017
    Publication date: January 24, 2019
    Inventors: Scott K. Pozder, Eng Chye Chua