Abstract: A Recursive bit-stream converter (Rebic) having digital low pass filter and multi-bit quantizer means in a feedback arrangement and means to serialize digital words obtain a non-integer Rebic factor via at least two quantizers that are successively operative to serialize their digital words to the output of the converter.

Abstract: Recursive bit-stream converter (Rebic) for converting a multi-bit digital input signal to a single bit digital output signal comprising a digital low pass filter and multi-bit quantizer means in a feedback arrangement and means to serialize the digital words of the quantizer means. To obtain a non-integer Rebic factor the quantizer means comprise at least two quantizers that are successively operative to serialize their digital words to the output of the converter.

Abstract: Method and arrangement for converting the sample rate of a higher sample rate discrete time signal to a lower sample rate discrete time signal or vice versa. A recursive signal processing algorithm with low pass filtering function is used, which entirely takes place at the lower sample rate.

Abstract: A pipeline AD converter comprising a cascade of AD-converter stages, whereby the sampling noise generated by a former stage of the cascade is AD-converted by the next stage in the cascade and the digital signals of the stages are combined to generate an error-reduced digital representation of the analog input signal. Applying the input signal to a synchronous ?? modulator and to an asynchronous ?? modulator and comparing the output signals of the ?? modulators generates the sampling noise.

Abstract: A pipeline AD converter comprising a cascade of AD-converter stages, whereby the sampling noise generated by a former stage of the cascade is AD-converted by the next stage in the cascade and the digital signals of the stages are combined to generate an error-reduced digital representation of the analog input signal. Applying the input signal to a synchronous &Sgr;&Dgr; modulator and to an asynchronous &Sgr;&Dgr; modulator and comparing the output signals of the &Sgr;&Dgr; modulators generates the sampling noise.

Abstract: An analog FIR-filter comprising an asynchronous &Sgr;&Dgr; modulator (AM) generating amplitude-discrete time-continuous pulses coupled to a sequence of delay cells (C1 . . . Cn) for delaying the amplitude-discrete time-continuous pulses. One or more output devices (O1, On, S1, Sn, I1, In) for low pass filtering of the delayed amplitude-discrete time-continuous pulses.

Abstract: Method and arrangement for converting the sample rate of a higher sample rate discrete time signal to a lower sample rate discrete time signal or vice versa. A recursive signal processing algorithm with low pass filtering function is used, which entirely takes place at the lower sample rate.

Abstract: Analog FIR-filter comprising an asynchronous &Sgr;&Dgr; modulator (AM) generating amplitude-discrete time-continuous pulses, a sequence of delay cells (C1 . . . Cn) for delaying said amplitude-discrete time-continuous pulses and means (O1, On, S1, Sn, I1, In) for low pass filtering the delayed amplitude-discrete time-continuous pulses.

Abstract: A D/A converter (DAC) is described having interpolation means (1) and filter means. Further the D/A converter comprises a noise shaper (3) implemented as a reduced sample rate (RSR) sigma delta modulator, and controlled by clock means. To further improve the operation of the D/A converter in an advantageous embodiment of the invention the filter means are implemented as polyphase FIR filter means.

Abstract: A method and arrangement for converting an analog input signal into a digital output signal. The analog input signal is converted into a duty cycle modulated square wave. For reducing the communication rate of the digital output signal a time frame of subsampling periods is created and, within each subsampling period, the position of samples, which approximately coincide with the transients of the square wave, is determined. The invention further provides an image sensor comprising a plurality of such arrangements.

Abstract: The invention relates to a synchronous sigma-delta modulator with a feedback loop which comprises an integrating filter followed by a polyphase sampler generating a plurality of phase shifted samples and an adder to add the plurality of phase shifted samples and to feed the added samples back to the input of the integrating filter.

Abstract: An analog to digital converter comprises an asynchronous sigma-delta modulator generating an asynchronous duty cycle modulated square wave, sampling means to synchronously sample the asynchronous square wave and a decimating digital filter to convert the samples from the sampling means into a desired PCM-format.

Abstract: An amplifier comprising an amplifier stage having an input terminal (1) for receiving an input signal; an output terminal (2) for supplying an output signal; an amplifier transistor (4); and a load (5). The load (5) comprises a first (T1) and a second (T2) field effect transistor. The current-voltage characteristic of the load (5) is similar to the diode characteristic of a conventional load formed by means of a diode-connected field effect transistor. The threshold voltage of the load (5) comprising the first (T1) and the second (T2) field effect transistor is much smaller than the threshold voltage of a conventional diode, which results in an improved output voltage swing of the amplifier stage.

Abstract: A sample rate converter is formed by a cascade configuration of a partial filter (20,22,32,26,28) and an equalizer (26,28,30,34) for equalizing the frequency characteristic of the partial filter. For obtaining a minimum-complexity equalizer when the complexity of the partial filter is minimized, the equalizer is arranged as a feedback system including in the feedback path an equalization filter that is substantially equal to the partial filter.

Abstract: Directly mixing synchronous receiver having an RF input (1) and a first signal path (S1) which is coupled thereto and which incorporates a first synchronous demodulator (3) and a first low-pass filter (4), and having a carrier regeneration circuit including a first phase-locked loop (Q) incorporating in a loop configuration a first phase detector (5) which is coupled to the RF input (1), a first loop filter (6) and a first voltage-controlled tuning oscillator (8) an output of which is coupled to the first phase detector (5), on the one hand, and to the first synchronous demodulator (3) via a phase shift circuit, on the other hand, for a direct demodulation of an RF reception signal to the frequency baseband. The local mixing carrier required for the direct synchronous demodulation should be accurately in phase or in antiphase with the carrier of a desired RF reception signal to be demodulated.

Abstract: An amplifier arrangement for reducing an unwanted d.c. offset of an amplitude-varying input signal, has a threshold circuit (A.sub.3, B.sub.3) and an amplifier stage (A.sub.1, B.sub.1) coupled thereto, which threshold circuit (A.sub.3, B.sub.3) is provided with a bistable trigger circuit (A.sub.4, B.sub.4). This bistable trigger circuit (A.sub.4, B.sub.4) reduces the d.c. level of the input signal or output signal of the amplifier stage (A.sub.1, B.sub.1) in a steplike manner when this d.c. level increases. The bistable trigger circuit (A.sub.4, B.sub.4) has a hysteresis which is larger than the maximum amplitude variation of the input signal as a result of the desired signal component, so that a linear amplification of this desired signal component is possible and, in the case of a non-varying d.c. level, variations of the input signal due to the desired signal component cannot give rise to a d.c. reduction.

Abstract: A clock generator for a pulse repeater of a receiver in a pulse transmission system comprises a forward filter (1) connected to its input (A), a difference former (2) whose positive input is connected to the output of the forward filter (1), a series arrangement connected between the output of the difference former (2) and the output (B) of the clock pulse generator and comprising a limiter (3), a time differentiator (4), a rectifier (5) and a narrow bandpass filter (10) in this order, and a feedback filter (6) connected between the output of the limiter (3) or the rectifier (5) and the negative input of the difference former (2). The limiter (3) is used to cancel intersymbol interference. The clock generator can be utilized in combination with a known pulse signal regenerator (1,7-9) of the decision feedback type to constitute a pulse repeater. Alternatively, a pulse repeater can be obtained by combining the clock generator with only a pulse regenerator (8, FIG.

Abstract: A tunable oscillator circuit provided with a pair of oscillator transistors whose bases are crosscoupled to the opposite collectors, and provided with a capacitance which is arranged between the emitters of the oscillator transistors, each emitter being AC-connected via an emitter current source to a reference voltage is disclosed. In order to considerably increase the tuning range without being limited in the choice of the output amplitude, a pair of buffer transistors in common base configuration is added whose two collectors are connected via a pair of collector resistors to a supply voltage and constitute an output of the tunable oscillator circuit, said pair of buffer transistors arranged in a cascode configuration with the pair of oscillator transistors by being coupled to the collectors of the oscillator transistors.

Abstract: A head-end for a signal distribution system with selection facility, includes a matrix (8) and a multiplexer (12) connected thereto for forming a multiplex signal. The head-end further comprises A/D converters (4-1 to .DELTA.-N) for converting the wide-band input signals into digital signals prior to supply to the matrix. The multiplexer comprises two amplitude modulators (13, 14) for the mutual quadrature amplitude modulation of a carrier (17) by two digital signals, and a summing means (18) for adding a digital signal in the base band to the modulated signal. A signal receiver for one of the modulated signals comprises a synchronous amplitude demodulator (21) connected to a synchronized carrier source (20) and also comprises means for digital-to-analog conversion (24).

Abstract: Head-end and receiver for a signal distribution system for signals having a wide frequency band and for accompanying signals having a narrow frequency band, such as the video signal and the sound signal of a television signal, respectively, digital signals being used for the distribution. The head-end comprises a first (4) and a second (5) A/D-converter for the signal having the wide frequency band and the signal having the narrow frequency band, respectively. The receiver comprises corresponding D/A-converters (13, 14). In order to avoid a specific frame structure and corresponding frame synchronization, the digital output signal of the second A/D-converter is modulated in a modulator (7) in the head-end on a subcarrier from a source (6) and thereafter added to the signal having the wide frequency band, and the combined signal is applied to the first A/D-converter (4) which is provided by a one-bit modulator.