Abstract: Certain aspects of the present disclosure are directed towards an apparatus for private data processing. The apparatus generally includes: a decryption component configured to receive encrypted data and generate decrypted data based on the encrypted data, wherein the decrypted data is marked as being secret; and one or more processors coupled to the decryption component and configured to process the decrypted data while maintaining the mark of being secret to yield secret processed data.

Abstract: A system and a method are disclosed for managing memory requests in a memory controller. The method includes storing a memory request in a request queue, the request queue comprising one or more request slots; determining if the memory request in the request queue is oversubscribed to a dedicated number of the request slots of a first information processor (IP); and copying the memory request from the request queue to a replay buffer comprising one or more replay slots in a case in which the memory request is oversubscribed to the first IP.

Abstract: A system includes a communication link coupled to an encoder and a decoder. The communication link includes a set of wires. The encoder is configured to encode a first block of input data to form a first codeword and to encode a second block of the input data to form a second codeword. The encoder is configured to generate a boundary bit based on at least one bit from each of the first codeword and the second codeword, and to send encoded data via the communication link. The encoded data includes a first set of bit values of the first codeword, a second set of bit values of the second codeword, and the boundary bit, which is located between the first set of bit values and the second set of bit values. The decoder is configured to decode the encoded data to generate a representation of the input data.

Abstract: A system includes a communication link coupled to an encoder and a decoder. The communication link includes a set of wires. The encoder is configured to encode a first block of input data to form a first codeword and to encode a second block of the input data to form a second codeword. The encoder is configured to generate a boundary bit based on at least one bit from each of the first codeword and the second codeword, and to send encoded data via the communication link. The encoded data includes a first set of bit values of the first codeword, a second set of bit values of the second codeword, and the boundary bit, which is located between the first set of bit values and the second set of bit values. The decoder is configured to decode the encoded data to generate a representation of the input data.

Abstract: A device includes a transmitter configured to obtain a particular set of bit values to be sent via a set of wires of a communication link. The transmitter is also configured to determine, based on a transition pattern associated with the particular set of bit values, whether to send the particular set of bit values during a single transmission period or during multiple transmission periods. The transmitter is further configured to send the particular set of bit values based on the determination.

Abstract: Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

Abstract: A method of controlling a trajectory of a perpendicular magnetization switching of a ferromagnetic layer using spin-orbit torques in the absence of any external magnetic field includes: injecting a charge current Je through a heavy-metal thin film disposed adjacent to a ferromagnetic layer to produce spin torques which drive a magnetization M out of an equilibrium state towards an in-plane of a nanomagnet; turning the charge current Je off after te seconds, where an effective field experienced by the magnetization of the ferromagnetic layer Heff is significantly dominated by and in-plane anisotropy Hkx, and where M passes a hard axis by precessing around the Heff; and passing the hard axis, where Heff is dominated by a perpendicular-to-the-plane anisotropy Hkz, and where M is pulled towards the new equilibrium state by precessing and damping around Heff, completing a magnetization switching.

Abstract: Aspects of the disclosure are directed to concurrent tensor processing with multiple processing engines. In accordance with one aspect, an apparatus including a common memory unit; a first processing engine coupled to the common memory unit, wherein the first processing engine is configured to access a portion of an input tensor and a portion of a kernel tensor from the common memory unit; and a second processing engine coupled to the common memory unit, wherein the first processing engine is further configured to send the portion of the input tensor and the portion of the kernel tensor to the second processing engine and wherein the second processing engine is configured to generate a portion of an output tensor based on the portion of the input tensor and on the portion of the kernel tensor.

Abstract: Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

Abstract: An apparatus, including: a memory; a matrix multiplier engine, comprising: an array of multiplier-accumulate units (MAUs) comprising: a first set of accumulators; and a second set of accumulators; and a controller configured to concurrently: cause a first set of resultant values in the first set of accumulators to be transferred to the memory pursuant to a first set of store instructions, wherein the first set of resultant values was generated pursuant to a first set of multiply-accumulate (MAC) operations performed by the set of multipliers and the first set of accumulators; and cause the set of multipliers and the second set of accumulators to perform a second set of MAC operations.

Abstract: A method of controlling a trajectory of a perpendicular magnetization switching of a ferromagnetic layer using spin-orbit torques in the absence of any external magnetic field includes: injecting a charge current Je through a heavy-metal thin film disposed adjacent to a ferromagnetic layer to produce spin torques which drive a magnetization M out of an equilibrium state towards an in-plane of a nanomagnet; turning the charge current Je off after te seconds, where an effective field experienced by the magnetization of the ferromagnetic layer Heff is significantly dominated by and in-plane anisotropy Hkx, and where M passes a hard axis by precessing around the Heff; and passing the hard axis, where Heff is dominated by a perpendicular-to-the-plane anisotropy Hkz, and where M is pulled towards the new equilibrium state by precessing and damping around Heff, completing a magnetization switching.

Abstract: A method of storing a sparse weight matrix for a trained artificial neural network in a circuit including a series of clusters. The method includes partitioning the sparse weight matrix into at least one first sub-block and at least one second sub-block. The first sub-block includes only zero-value weights and the second sub-block includes non-zero value weights. The method also includes assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the series of clusters of the circuit. The circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector during an inference process utilizing the artificial neural network. The sub-blocks containing all zero elements are power gated, thereby reducing overall energy consumption for inference.

Abstract: Selective refresh techniques for memory devices are disclosed. In one aspect, a memory device that is used with an application that has frequent repeated read or write commands to certain memory segments may be able to set a flag or similar indication that exempts these certain memory segments from being actively refreshed. By exempting these memory segments from being actively refreshed, these memory segments are continuously available, thereby improving performance. Likewise, because these memory segments are so frequently the subject of a read or write command, these memory segments are indirectly refreshed through the execution of the read or write command.

Abstract: The energy consumed by data transfer in a computing device may be reduced by transferring data that has been encoded in a manner that reduces the number of one “1” data values, the number of signal level transitions, or both. A data destination component of the computing device may receive data encoded in such a manner from a data source component of the computing device over a data communication interconnect, such as an off-chip interconnect. The data may be encoded using minimum Hamming weight encoding, which reduces the number of one “1” data values. The received data may be decoded using minimum Hamming weight decoding. For other computing devices, the data may be encoded using maximum Hamming weight encoding, which increases the number of one “1” data values while reducing the number of zero “0” values, if reducing the number of zero values reduces energy consumption.

Abstract: A method of controlling a trajectory of a perpendicular magnetization switching of a ferromagnetic layer using spin-orbit torques in the absence of any external magnetic field includes: injecting a charge current Je through a heavy-metal thin film disposed adjacent to a ferromagnetic layer to produce spin torques which drive a magnetization M out of an equilibrium state towards an in-plane of a nanomagnet; turning the charge current Je off after te seconds, where an effective field experienced by the magnetization of the ferromagnetic layer Heff is significantly dominated by and in-plane anisotropy Hkx, and where M passes a hard axis by precessing around the Heff; and passing the hard axis, where Heff is dominated by a perpendicular-to-the-plane anisotropy Hkz, and where M is pulled towards the new equilibrium state by precessing and damping around Heff, completing a magnetization switching.

Abstract: The energy consumed by data transfer in a computing device may be reduced by transferring data that has been encoded in a manner that reduces the number of one “1” data values, the number of signal level transitions, or both. A data destination component of the computing device may receive data encoded in such a manner from a data source component of the computing device over a data communication interconnect, such as an off-chip interconnect. The data may be encoded using minimum Hamming weight encoding, which reduces the number of one “1” data values. The received data may be decoded using minimum Hamming weight decoding. For other computing devices, the data may be encoded using maximum Hamming weight encoding, which increases the number of one “1” data values while reducing the number of zero “0” values, if reducing the number of zero values reduces energy consumption.

Abstract: A memory device includes a storage unit array and a controller. The storage unit array contains storage units arranged in M rows and N columns and has M word lines and N bit line pairs. Each of the N bit line pairs includes a bit line and a source line. In operation, after obtaining Q rows of data that are to be written into Q rows of storage units in the storage unit array, the controller writes a first value into each of storage units in a column j in P columns of storage units. The controller then determines to-be-written rows in the Q rows of data, and writes in parallel a second value into each of storage units of the to-be-written rows in the storage units in the column j.

Abstract: A method of controlling a trajectory of a perpendicular magnetization switching of a ferromagnetic layer using spin-orbit torques in the absence of any external magnetic field includes: injecting a charge current Je through a heavy-metal thin film disposed adjacent to a ferromagnetic layer to produce spin torques which drive a magnetization M out of an equilibrium state towards an in-plane of a nanomagnet; turning the charge current Je off after te seconds, where an effective field experienced by the magnetization of the ferromagnetic layer Heff is significantly dominated by and in-plane anisotropy Hkx, and where M passes a hard axis by precessing around the Heff; and passing the hard axis, where Heff is dominated by a perpendicular-to-the-plane anisotropy Hkz, and where M is pulled towards the new equilibrium state by precessing and damping around Heff, completing a magnetization switching.

Abstract: A base element for switching a magnetization state of a nanomagnet includes a heavy-metal nanostrip having a surface. A ferromagnetic nanomagnet is disposed adjacent to the surface. The ferromagnetic nanomagnet includes a shape having a long axis and a short axis. The ferromagnetic nanomagnet has both a perpendicular-to-the-plane anisotropy Hkz and an in-plane anisotropy Hkx and the ferromagnetic nanomagnet has a first magnetization equilibrium state and a second magnetization equilibrium state. The first magnetization equilibrium state or the second magnetization equilibrium state is settable by a flow of electrical charge through the heavy-metal nanostrip. A direction of flow of the electrical charge through the heavy-metal nanostrip includes an angle ? with respect to the short axis of the nanomagnet.

Abstract: Methods and apparatus to provide virtualized vector processing are described. In one embodiment, one or more operations corresponding to a virtual vector request are distributed to one or more processor cores for execution.