Patents by Inventor Enis Aykut Dengi

Enis Aykut Dengi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240029138
    Abstract: A visual tracking system for tracking and identifying persons within a monitored location, comprising a plurality of cameras and a visual processing unit, each camera produces a sequence of video frames depicting one or more of the persons, the visual processing unit is adapted to maintain a coherent track identity for each person across the plurality of cameras using a combination of motion data and visual featurization data, and further determine demographic data and sentiment data using the visual featurization data, the visual tracking system further having a recommendation module adapted to identify a customer need for each person using the sentiment data of the person in addition to context data, and generate an action recommendation for addressing the customer need, the visual tracking system is operably connected to a customer-oriented device configured to perform a customer-oriented action in accordance with the action recommendation.
    Type: Application
    Filed: February 13, 2023
    Publication date: January 25, 2024
    Inventors: Abraham Othman, Enis Aykut Dengi, Ishan Krishna Agrawal, Jeff Kershner, Peter Martinez, Paul Mills, Abhinav Yarlagadda
  • Patent number: 11580648
    Abstract: A visual tracking system for tracking and identifying persons within a monitored location, comprising a plurality of cameras and a visual processing unit, each camera produces a sequence of video frames depicting one or more of the persons, the visual processing unit is adapted to maintain a coherent track identity for each person across the plurality of cameras using a combination of motion data and visual featurization data, and further determine demographic data and sentiment data using the visual featurization data, the visual tracking system further having a recommendation module adapted to identify a customer need for each person using the sentiment data of the person in addition to context data, and generate an action recommendation for addressing the customer need, the visual tracking system is operably connected to a customer-oriented device configured to perform a customer-oriented action in accordance with the action recommendation.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: February 14, 2023
    Inventors: Abraham Othman, Enis Aykut Dengi, Ishan Agrawal, Jeff Kershner, Peter Martinez, Paul Mills, Abhinav Yarlagadda
  • Publication number: 20210304421
    Abstract: A visual tracking system for tracking and identifying persons within a monitored location, comprising a plurality of cameras and a visual processing unit, each camera produces a sequence of video frames depicting one or more of the persons, the visual processing unit is adapted to maintain a coherent track identity for each person across the plurality of cameras using a combination of motion data and visual featurization data, and further determine demographic data and sentiment data using the visual featurization data, the visual tracking system further having a recommendation module adapted to identify a customer need for each person using the sentiment data of the person in addition to context data, and generate an action recommendation for addressing the customer need, the visual tracking system is operably connected to a customer-oriented device configured to perform a customer-oriented action in accordance with the action recommendation.
    Type: Application
    Filed: May 3, 2021
    Publication date: September 30, 2021
    Inventors: Abraham Othman, Enis Aykut Dengi, Ishan Agrawal, Jeff Kershner, Peter Martinez, Paul Mills, Abhinav Yarlagadda
  • Patent number: 11024043
    Abstract: A visual tracking system for tracking and identifying persons within a monitored location, comprising a plurality of cameras and a visual processing unit, each camera produces a sequence of video frames depicting one or more of the persons, the visual processing unit is adapted to maintain a coherent track identity for each person across the plurality of cameras using a combination of motion data and visual featurization data, and further determine demographic data and sentiment data using the visual featurization data, the visual tracking system further having a recommendation module adapted to identify a customer need for each person using the sentiment data of the person in addition to context data, and generate an action recommendation for addressing the customer need, the visual tracking system is operably connected to a customer-oriented device configured to perform a customer-oriented action in accordance with the action recommendation.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 1, 2021
    Inventors: Abraham Othman, Enis Aykut Dengi, Ishan Agrawal, Jeff Kershner, Peter Martinez, Paul Mills, Abhinav Yarlagadda
  • Patent number: 8380468
    Abstract: A system, method, and software program for facilitating the assignment of cell specifications to a plurality of cells of a system design. The methods include generating a plurality of candidate cell specifications that meet the specification for the system design. In one embodiment, the method entails using information related to intra-range preference for cell specifications to generate a set of alternative system pareto-optimal solutions which define a boundary of a region of candidate cell specifications. In another embodiment, the method entails generating a substantially uniform set of candidate cell specifications using a prediction-based performance model, such as support vector regression model or cluster-weighted model, an optimizing algorithm such as conjugate-gradient or Markov Chain Monte Carlo Method, and a sample density model.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: February 19, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Stephen McCracken, Enis Aykut Dengi, Xuejin Wang
  • Patent number: 7957949
    Abstract: A method of system design, and more particularly a method of designing systems that achieve a set of performance goals using a hierarchically partitioned system representation wherein performance simulations are performed at multiple levels within the hierarchy and are combined to simulate a system level result in order to reduce the aggregate time required for performance simulation.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: June 7, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pero Subasic, Enis Aykut Dengi
  • Patent number: 7933748
    Abstract: A system, method, and software program for facilitating the assignment of cell specifications to a plurality of cells of a system design. The methods include generating a plurality of candidate cell specifications that meet the specification for the system design. In one embodiment, the method entails using information related to intra-range preference for cell specifications to generate a set of alternative system pareto-optimal solutions which define a boundary of a region of candidate cell specifications. In another embodiment, the method entails generating a substantially uniform set of candidate cell specifications using a prediction-based performance model, such as support vector regression model or cluster-weighted model, an optimizing algorithm such as conjugate-gradient or Markov Chain Monte Carlo Method, and a sample density model.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: April 26, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Stephen McCracken, Enis Aykut Dengi, Xuejin Wang
  • Patent number: 7735048
    Abstract: Methods achieve fast parasitic closure in IC (integrated circuit) synthesis flow with particular application to RFIC (radio frequency integrated circuit) synthesis flow. Parasitic corners generated based on earlier layout statistics are incorporated into circuit resizing to enable parasitic robust designs. The worst-case parasitic corners are generated efficiently without expensive statistical computations. A performance-driven placement with simultaneous fast rough routing and device tuning generates high quality placements and compensates for layout induced performance degradations. A regression-tree based macromodeling methodology is introduced for modeling of electrical performances to enable true performance-driven layout synthesis. To improve sampling quality, an annealing-based placer can be used to perform sampling. The modeling methodology can be adapted to include automatically adjusting the device tuning ranges to meet certain model accuracy requirements.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: June 8, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gang Zhang, Enis Aykut Dengi, Ronald A. Rohrer
  • Patent number: 7689949
    Abstract: A method of modeling an integrated circuit includes: specifying a layout for the integrated circuit, wherein the layout includes a plurality of devices arranged in a plurality of layers and a plurality of connections between the layers; specifying locations for a source point and an observation point for the integrated circuit; determining a plurality of static images for the source point and the observation point; determining a plurality of discrete complex images for the source point and the observation point; determining a Green's-function value for the source point and the observation point by combining the static images and the discrete complex images; and saving at least some values based on the Green's-function value.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: March 30, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Feng Ling, Ben Song, Vladimir I. Okhmatovski, Enis Aykut Dengi
  • Patent number: 7657416
    Abstract: A method of system design, and more particularly a method of designing systems that achieve a set of performance goals using a hierarchically partitioned system representation wherein performance simulations are performed at multiple levels within the hierarchy and are combined to simulate a system level result in order to reduce the aggregate time required for performance simulation.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: February 2, 2010
    Assignee: Cadence Design Systems, Inc
    Inventors: Pero Subasic, Enis Aykut Dengi
  • Patent number: 7539961
    Abstract: A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for relating currents and voltages can be incrementally adapted from other designs or design elements in applications including mixed-signal, analog and RF (radio frequency) circuits.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: May 26, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Enis Aykut Dengi, Feng Ling, Ben Song, Warren Harris
  • Patent number: 7506294
    Abstract: A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for relating currents and voltages can be incrementally adapted from other designs or design elements in applications including mixed-signal, analog and RF (radio frequency) circuits.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: March 17, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Enis Aykut Dengi, Feng Ling, Ben Song, Warren Harris
  • Patent number: 7356784
    Abstract: A method determining an IC (integrated circuit) design includes: determining one or more design variables, wherein the one or more design variables include one or more device variables and one or more weights; determining one or more net lengths and one or more layout metrics from the one or more device variables and the one or more weights; and determining the IC design from the one or more device variables and the one or more net lengths. The IC design includes a schematic and a layout. The process can be repeated as needed according to performance criteria that may include circuit performance metrics and layout performance metrics.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: April 8, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Enis Aykut Dengi, Stephen McCracken, Michael R. Kelly, Matthew B. Phelps, Ibraz Mohammed
  • Publication number: 20080077898
    Abstract: The invention is a method of placement of components and networks (nets), utilized for interconnecting the components, of a circuit layout. The method includes forming for electrical devices, pads (or lands) and networks (nets) of a circuit layout a listing of the positions thereof with respect to one another, connections therebetween and the orientation of each net or subnet thereof in the circuit layout. The thus formed list is processed subject to at least one objective regarding the size of the circuit layout, whereupon a placement of the electrical devices and the pads is determined simultaneously with the placement of the networks.
    Type: Application
    Filed: September 27, 2006
    Publication date: March 27, 2008
    Applicant: Cadence Design Systems, Inc.
    Inventors: Pero Subasic, Xuejin Wang, Enis Aykut Dengi, Ibraz H. Mohammed
  • Patent number: 7139987
    Abstract: In an automated integrated circuit design, if the performances of a layout of circuit devices are not within predetermined tolerances of performance specifications, at least one of the circuit devices is resized or repositioned and an updated value of a device parameter for each resized or repositioned circuit device is determined. A difference between the initial and updated value of each device parameter is then determined and each difference is combined with a ratio formed from changes in the value of one of the device parameters and changes in the value of one of the performances affected by the device parameter. The result of this combination is then combined with the initial value of the performance to determine an updated value therefor.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: November 21, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gang Zhang, Enis Aykut Dengi, Ronald A. Rohrer
  • Patent number: 7127688
    Abstract: To estimate a distribution of voltages or currents in the layers of a multi-layer circuit, an exemplary current flow in each layer is discretized into a number of current vector elements and at least one scalar charge element related to the charge associated with each current vector element. A first distribution of voltages induced in each circuit layer is determined from current vector elements in all of the circuit layers. A second distribution of voltages induced in each circuit layer is determined from the scalar charge elements in all of the circuit layers. For each circuit layer, the first and second distributions of voltages induced therein are combined to determine an actual distribution of voltages in the circuit layer.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: October 24, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Feng Ling, Vladimir I. Okhmatovski, Enis Aykut Dengi
  • Publication number: 20040010764
    Abstract: In an automated integrated circuit design, if the performances of a layout of circuit devices are not within predetermined tolerances of performance specifications, at least one of the circuit devices is resized or repositioned and an updated value of a device parameter for each resized or repositioned circuit device is determined. A difference between the initial and updated value of each device parameter is then determined and each difference is combined with a ratio formed from changes in the value of one of the device parameters and changes in the value of one of the performances affected by the device parameter. The result of this combination is then combined with the initial value of the performance to determine an updated value therefor.
    Type: Application
    Filed: July 11, 2003
    Publication date: January 15, 2004
    Applicant: Neolinear, Inc.
    Inventors: Gang Zhang, Enis Aykut Dengi, Ronald A. Rohrer