Abstract: An array substrate motherboard includes a substrate including a plurality of gate lines, a plurality of gate line driving leads, a plurality of data lines, and a plurality of data line driving leads; a plurality of gate line testing leads; a plurality of data line testing leads and a plurality of data line driving leads; a plurality of gate line testing pads; a plurality of data line testing pads; and an insulating layer arranged between the data line testing leads and the data line driving leads in the trimming region. A respective one of the plurality of data line testing pads is connected with a respective one of the plurality of data line testing leads. A respective one of the plurality of data line driving leads is connected with one of the plurality of data line testing leads that penetrate through the insulating layer.

Abstract: An array substrate motherboard includes a substrate including a plurality of gate lines, a plurality of gate line driving leads, a plurality of data lines, and a plurality of data line driving leads; a plurality of gate line testing leads; a plurality of data line testing leads and a plurality of data line driving leads; a plurality of gate line testing pads; a plurality of data line testing pads; and an insulating layer arranged between the data line testing leads and the data line driving leads in the trimming region. A respective one of the plurality of data line testing pads is connected with a respective one of the plurality of data line testing leads. A respective one of the plurality of data line driving leads is connected with one of the plurality of data line testing leads that penetrate through the insulating layer.

Abstract: In some embodiments, an array substrate motherboard and a fabricating method thereof are provided. The method includes: providing a substrate including multiple gate lines, gate driving leads, data lines, and data driving leads, each gate line corresponds to one gate driving lead, each data line corresponds to one data driving lead; forming multiple gate line testing leads, each gate line testing lead is connected with a gate driving lead; forming multiple data line testing leads, each data line testing lead is connected with a subset of the multiple data driving leads; forming multiple gate line testing pads, each gate line testing pad is connected with a gate line testing lead; forming multiple data line testing pads, each data line testing pad is connected with two data line testing leads; and using the gate line testing pads and gate line testing pads to test the gate lines and data lines.

Abstract: In some embodiments, an array substrate motherboard and a fabricating method thereof are provided. The method includes: providing a substrate including multiple gate lines, gate driving leads, data lines, and data driving leads, each gate line corresponds to one gate driving lead, each data line corresponds to one data driving lead; forming multiple gate line testing leads, each gate line testing lead is connected with a gate driving lead; forming multiple data line testing leads, each data line testing lead is connected with a subset of the multiple data driving leads; forming multiple gate line testing pads, each gate line testing pad is connected with a gate line testing lead; forming multiple data line testing pads, each data line testing pad is connected with two data line testing leads; and using the gate line testing pads and gate line testing pads to test the gate lines and data lines.