Patents by Inventor Ennio Salemi
Ennio Salemi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240095195Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Alok Kumar MATHUR, Ennio SALEMI, Drew Eric WINGARD, Valerio CATALANO
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Patent number: 11868281Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.Type: GrantFiled: August 8, 2022Date of Patent: January 9, 2024Assignee: Meta Platforms Technologies, LLCInventors: Alok Kumar Mathur, Ennio Salemi, Drew Eric Wingard, Valerio Catalano
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Publication number: 20220391331Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.Type: ApplicationFiled: August 8, 2022Publication date: December 8, 2022Inventors: Alok Kumar Mathur, Ennio Salemi, Drew Eric Wingard, Valerio Catalano
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Patent number: 11409671Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.Type: GrantFiled: December 19, 2019Date of Patent: August 9, 2022Assignee: Facebook Technologies, LLCInventors: Alok Kumar Mathur, Ennio Salemi, Drew Eric Wingard, Valerio Catalano
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Publication number: 20220004328Abstract: The disclosure describes techniques for hierarchical power management of memory of an artificial reality system to reduce power consumption by the memory. An example device may be a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content for display. The device includes memory divided into multiple memory blocks configurable to operate in a plurality of power modes. The device also includes memory block controllers controlling memory blocks. Each memory block controller controls which power mode in which the corresponding memory block is to operate, independent of any of the other memory blocks. The device includes a memory power controller configured to configure control registers of the memory block controllers to direct the memory block controllers to select one of the plurality of power modes for the memory blocks when the memory blocks are not being accessed.Type: ApplicationFiled: July 31, 2020Publication date: January 6, 2022Inventors: Shrirang Madhav Yardi, Gregory Edward Ehmann, Ennio Salemi, George Spatz, Jeffrey Ryden
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Publication number: 20210089475Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.Type: ApplicationFiled: December 19, 2019Publication date: March 25, 2021Inventors: Alok Kumar Mathur, Ennio Salemi, Drew Eric Wingard, Valerio Catalano
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Patent number: 9946652Abstract: A memory management system for managing a memory and includes a multi-stage memory management unit including control circuitry and cache memory. The cache memory may have a respective translation look-aside buffer for each stage of the multi-stage memory management unit. The control circuitry may be configured to generate a blank data request including a virtual address and information that specifies that data is not to be read from the memory, perform address translations based on the generated blank data request in multiple stages until a physical address is obtained, and discard the blank data request.Type: GrantFiled: September 15, 2014Date of Patent: April 17, 2018Assignee: STMicroelectronics International N.V.Inventors: Gilles Ries, Ennio Salemi, Sana Ben Alaya
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Patent number: 9436610Abstract: A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount. The cache unit may store the second amount of further address translation information for use with data requests that are subsequent to a current data request, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit.Type: GrantFiled: August 21, 2014Date of Patent: September 6, 2016Assignee: STMicroelectronics International N.V.Inventors: Gilles Ries, Ennio Salemi, Sana Ben Alaya
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Patent number: 9407551Abstract: The method of transferring data between a first and a second set of elements via a switch that includes a set of paths each associated with a weighting coefficient representing a data stream for each path. The method includes a credit flow control between the first set of elements and the switch and a credit flow control between the switch and the second set of elements. An available credit coefficient is computed for each element of the first set on the basis of a credit allocated by each element of the second set and of the weighting coefficient of each path.Type: GrantFiled: January 29, 2009Date of Patent: August 2, 2016Assignee: ST-Ericsson SAInventor: Ennio Salemi
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Publication number: 20150081983Abstract: A memory management system for managing a memory and includes a multi-stage memory management unit including control circuitry and cache memory. The cache memory may have a respective translation look-aside buffer for each stage of the multi-stage memory management unit. The control circuitry may be configured to generate a blank data request including a virtual address and information that specifies that data is not to be read from the memory, perform address translations based on the generated blank data request in multiple stages until a physical address is obtained, and discard the blank data request.Type: ApplicationFiled: September 15, 2014Publication date: March 19, 2015Applicant: STMicroelectronics International N.V.Inventors: Gilles Ries, Ennio Salemi, Sana Ben Alaya
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Publication number: 20150058578Abstract: A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount. The cache unit may store the second amount of further address translation information for use with data requests that are subsequent to a current data request, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit.Type: ApplicationFiled: August 21, 2014Publication date: February 26, 2015Applicant: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Gilles Ries, Ennio Salemi, Sana Ben Alaya
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Publication number: 20090192939Abstract: The method of transferring data between a first and a second set of elements via a switch that includes a set of paths each associated with a weighting coefficient representing a data stream for each path. The method includes a credit flow control between the first set of elements and the switch and a credit flow control between the switch and the second set of elements. An available credit coefficient is computed for each element of the first set on the basis of a credit allocated by each element of the second set and of the weighting coefficient of each path.Type: ApplicationFiled: January 29, 2009Publication date: July 30, 2009Applicant: STMicroelectronics SAInventor: Ennio Salemi