Patents by Inventor Ennis T. Ogawa
Ennis T. Ogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10629504Abstract: A die edge crack and delamination detection device includes a semiconductor device including an IC active area surrounded by at least one mechanical protection barrier (MPB); one or more metallization layers stacked on the IC active area; a plurality of passive electronic devices placed within the metallization layers at respective predetermined distances from the MPB; and a detection circuit having circuitry. The circuitry is configured to determine a specific metallization layer in which a crack or a delamination is encroaching from an edge of the semiconductor device, determine a lateral distance of a lead end of the crack or the delamination from the MPB, and determine a rate of approach of the crack or the delamination encroaching towards the MPB, via a nominal change in an electrical measurement of at least one of the passive electronic devices.Type: GrantFiled: May 3, 2017Date of Patent: April 21, 2020Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Ennis T. Ogawa, Yusang Lin, Liming Tsau
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Publication number: 20170323835Abstract: A die edge crack and delamination detection device includes a semiconductor device including an IC active area surrounded by at least one mechanical protection barrier (MPB); one or more metallization layers stacked on the IC active area; a plurality of passive electronic devices placed within the metallization layers at respective predetermined distances from the MPB; and a detection circuit having circuitry. The circuitry is configured to determine a specific metallization layer in which a crack or a delamination is encroaching from an edge of the semiconductor device, determine a lateral distance of a lead end of the crack or the delamination from the MPB, and determine a rate of approach of the crack or the delamination encroaching towards the MPB, via a nominal change in an electrical measurement of at least one of the passive electronic devices.Type: ApplicationFiled: May 3, 2017Publication date: November 9, 2017Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Ennis T. OGAWA, Yusang LIN, Liming TSAU
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Patent number: 7888776Abstract: One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an integrated circuit chip die. The scribe seal integrity comprises a scribe seal structure that extends along at least a portion of the periphery of the integrated chip die and a detector test structure. The detector test structure and the scribe seal form an electrical system configured to be accessed for a monitoring of one or more electrical parameters to determine and characterize scribe seal integrity of the integrated circuit chip die. The results of the electric measurements are analyzed for statistically relevant reliability characterization. Other methods and circuits are also disclosed.Type: GrantFiled: June 30, 2008Date of Patent: February 15, 2011Assignee: Texas Instruments IncorporatedInventors: Ennis T. Ogawa, Honglin Guo, Joe W. McPherson
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Publication number: 20090321734Abstract: One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an integrated circuit chip die. The scribe seal integrity comprises a scribe seal structure that extends along at least a portion of the periphery of the integrated chip die and a detector test structure. The detector test structure and the scribe seal form an electrical system configured to be accessed for a monitoring of one or more electrical parameters to determine and characterize scribe seal integrity of the integrated circuit chip die. The results of the electric measurements are analyzed for statistically relevant reliability characterization. Other methods and circuits are also disclosed.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Applicant: Texas Instruments IncorporatedInventors: Ennis T. Ogawa, Honglin Guo, Joe W. McPherson
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Publication number: 20080246491Abstract: In a method and system for testing a presence of a crack (240) in a device under test (DUT) (190), a test system includes a bridge circuit (BC) (120) coupled to an electrical signal source (ESS) (110) capable of generating an electrical signal (102). The BC (120) includes four impedances that are coupled in a bridge structure having two floating nodes (132, 134). The DUT (190) includes a test bond pad (TBP) (192) and an access bond pad (ABP) (194). An impedance measurable across the TBP (192) and the ABP (194) is selectable as one of the four impedances. A stimulus (140) is provided to the DUT (190) to induce stress. A sensor (130) coupled across the two floating nodes (132, 134) detects a change in a value of the electrical signal measured across the two floating nodes (132, 134) in response to the stimulus (140). The change is triggered by the presence of the crack (240) under the TBP (192) caused by the stress, the crack (240) changing the impedance.Type: ApplicationFiled: April 6, 2007Publication date: October 9, 2008Applicant: Texas Instruments IncorporatedInventors: Ennis T. Ogawa, Daryl R. Heussner, Charles A. Odegard
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Patent number: 7033924Abstract: Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device typically comprises a first interconnect (402, 502), and a second interconnect (404, 504). The primary structure is disposed between the first and second interconnects to electrically intercouple them. An active diffusion volume (410, 514) is determined, within which the primary structure is located. A buffer structure (408, 508) is disposed upon the first interconnect in proximity to the primary structure and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary structure and the first interconnect.Type: GrantFiled: September 16, 2003Date of Patent: April 25, 2006Assignee: Texas Instruments IncorporatedInventors: Ennis T. Ogawa, Joe W. McPherson
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Patent number: 6737351Abstract: Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device typically comprises a first interconnect (402, 502), and a second interconnect (404, 504). The primary structure is disposed between the first and second interconnects to electrically intercouple them. An active diffusion volume (410, 514) is determined, within which the primary structure is located. A buffer structure (408, 508) is disposed upon the first interconnect in proximity to the primary structure and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary structure and the first interconnect.Type: GrantFiled: April 1, 2002Date of Patent: May 18, 2004Assignee: Texas Instruments IncorporatedInventors: Ennis T. Ogawa, Joe W. McPherson
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Publication number: 20040041274Abstract: Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device typically comprises a first interconnect (402, 502), and a second interconnect (404, 504). The primary structure is disposed between the first and second interconnects to electrically intercouple them. An active diffusion volume (410, 514) is determined, within which the primary structure is located. A buffer structure (408, 508) is disposed upon the first interconnect in proximity to the primary structure and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary structure and the first interconnect.Type: ApplicationFiled: September 16, 2003Publication date: March 4, 2004Inventors: Ennis T. Ogawa, Joe W. McPherson
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Publication number: 20030122260Abstract: Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device typically comprises a first interconnect (402, 502), and a second interconnect (404, 504). The primary structure is disposed between the first and second interconnects to electrically intercouple them. An active diffusion volume (410, 514) is determined, within which the primary structure is located. A buffer structure (408, 508) is disposed upon the first interconnect in proximity to the primary structure and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary structure and the first interconnect.Type: ApplicationFiled: April 1, 2002Publication date: July 3, 2003Inventors: Ennis T. Ogawa, Joe W. McPherson