Abstract: Technology is disclosed for dynamically assigning apps to non-volatile memory based on monitoring the apps' usage of memory resources. For a memory system having a high endurance section, such as binary (or single level cell, SLC) memory, and a lower endurance section, such as multi-level cell (MLC) memory, an app, including both the code for executing the app and the associated data payload, may initially be stored in the lower endurance section. The memory system monitors the activity of the app for high levels of activity and, if the app is being frequently written, the memory system notifies the host. In response, the host can request the memory system to move the app or just its associated payload to the high endurance section.

Abstract: Technology is disclosed for dynamically assigning apps to non-volatile memory based on monitoring the apps' usage of memory resources. For a memory system having a high endurance section, such as binary (or single level cell, SLC) memory, and a lower endurance section, such as multi-level cell (MLC) memory, an app, including both the code for executing the app and the associated data payload, may initially be stored in the lower endurance section. The memory system monitors the activity of the app for high levels of activity and, if the app is being frequently written, the memory system notifies the host. In response, the host can request the memory system to move the app or just its associated payload to the high endurance section.

Abstract: Technology that provides security for a requestor of data stored in a non-volatile memory device is disclosed. In one aspect, the non-volatile memory device provides data on a host interface only if a digest for the data matches an expected digest for the data. The non-volatile memory device may store expected digests for data for various logical addresses. Upon receiving a request on the host interface to read data for a logical address, the non-volatile memory device may access the data for the logical address, compute a digest for the accessed data, and compare the computed digest with the expected digest. The non-volatile memory device provides the accessed data on the host interface only if the computed digest matches the expected digest, in one aspect. The non-volatile memory device may be used to provide a secure boot of a host.

Abstract: A non-volatile memory device uses physical authentication to enable the secure programming of a boot partition, when the boot partition is write protected. This physical authentication can also be used to enable other features/functions.

Abstract: Technology that provides security for a requestor of data stored in a non-volatile memory device is disclosed. In one aspect, the non-volatile memory device provides data on a host interface only if a digest for the data matches an expected digest for the data. The non-volatile memory device may store expected digests for data for various logical addresses. Upon receiving a request on the host interface to read data for a logical address, the non-volatile memory device may access the data for the logical address, compute a digest for the accessed data, and compare the computed digest with the expected digest. The non-volatile memory device provides the accessed data on the host interface only if the computed digest matches the expected digest, in one aspect. The non-volatile memory device may be used to provide a secure boot of a host.

Abstract: A non-volatile memory device uses physical authentication to enable the secure programming of a boot partition, when the boot partition is write protected. This physical authentication can also be used to enable other features/functions.

Abstract: A storage module and method for adaptive burst mode are provided. In one embodiment, a storage module is provided comprising a memory and a controller. The controller is configured to receive a plurality of write commands from a host controller in communication with the storage module, store the plurality of write commands in a command queue in the storage module, and choose one of a plurality of burst modes in which to operate the memory based on how many write commands are stored in the command queue.

Abstract: A storage module and method for adaptive burst mode are provided. In one embodiment, a storage module is provided comprising a memory and a controller. The controller is configured to receive a plurality of write commands from a host controller in communication with the storage module, store the plurality of write commands in a command queue in the storage module, and choose one of a plurality of burst modes in which to operate the memory based on how many write commands are stored in the command queue.

Abstract: A non-volatile memory chip package is prepared for surface mounting to a substrate in a solder reflow process by programming erased blocks to higher threshold voltage levels, to improve data retention for blocks which are preloaded with content, such as by an electronic device manufacturer. Following the surface mounting, the previously-erased blocks are returned to the erased state. The threshold voltage of storage elements of the preloaded blocks can change during the surface mounting process due to a global charge effect phenomenon. The effect is most prominent for higher state storage elements which are surrounded by erased blocks, in a chip for which the wafer backside was thinned and polished. The erased blocks can be programmed using a single program pulse without performing a verify operation, as a wide threshold voltage distribution is acceptable.

Abstract: A non-volatile memory chip package is prepared for surface mounting to a substrate in a solder reflow process by programming erased blocks to higher threshold voltage levels, to improve data retention for blocks which are preloaded with content, such as by an electronic device manufacturer. Following the surface mounting, the previously-erased blocks are returned to the erased state. The threshold voltage of storage elements of the preloaded blocks can change during the surface mounting process due to a global charge effect phenomenon. The effect is most prominent for higher state storage elements which are surrounded by erased blocks, in a chip for which the wafer backside was thinned and polished. The erased blocks can be programmed using a single program pulse without performing a verify operation, as a wide threshold voltage distribution is acceptable.