Abstract: The invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows and columns, each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line through a selection element of the byte switch type, and each cell being connected to a respective control column through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase.

Abstract: Non-volatile, electrically alterable semiconductor memory, including at least one two-dimensional array of memory cells with a plurality of rows and a plurality of columns, column selection circuitry for selecting columns among the plurality of columns, and a write circuit for simultaneously writing a first number of memory cells. A plurality of doped semiconductor regions is provided, extending transversally to the rows and subdividing a set of memory cells of each row in a corresponding plurality of subsets of memory cells, each subset of memory cells including memory cells of the row formed in a respective doped semiconductor region distinct from the remaining doped semiconductor regions and defining an elementary memory block that can be individually erased.

Abstract: The invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows and columns, each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line through a selection element of the byte switch type, and each cell being connected to a respective control column through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase.

Abstract: The invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows and columns, each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line through a selection element of the byte switch type, and each cell being connected to a respective control column through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase.

Abstract: The programming method comprises supplying a turnoff voltage to the source terminal of the selected cells when writing the cells. The turnoff voltage is a positive voltage of greater amplitude than the absolute value of the threshold voltage of the most written cell, i.e., the most depleted cell, taking into account the body effect. For example, the turnoff voltage may be 1 V greater than the absolute value of the threshold voltage of the most written cell. Advantageously, the turnoff voltage may be 5-6 V; to take into account the process, supply, and temperature variations, the turnoff voltage may be 7-8 V. The programming method is advantageously applicable to EEPROM memory devices with divided source lines, so as to apply the turnoff voltage only to the addressed byte or bytes, or to the page containing the addressed byte.

Abstract: Non-volatile, electrically alterable semiconductor memory, including at least one two-dimensional array of memory cells with a plurality of rows and a plurality of columns, column selection circuitry for selecting columns among the plurality of columns, and a write circuit for simultaneously writing a first number of memory cells. A plurality of doped semiconductor regions is provided, extending transversally to the rows and subdividing a set of memory cells of each row in a corresponding plurality of subsets of memory cells, each subset of memory cells including memory cells of the row formed in a respective doped semiconductor region distinct from the remaining doped semiconductor regions and defining an elementary memory block that can be individually erased.

Abstract: A test structure is formed by an array of memory cells connected in parallel and including each a memory transistor and a select transistor connected in series. The gate terminals of the select transistors of all memory cells are biased to a value next to the threshold voltage of the select transistors. Therefore, in each memory cell, the drain current is limited by the memory transistor for control gate voltages below the threshold voltage of the memory transistor, and by the select transistor at higher voltages; for high control gate voltages, the drain current is clamped to a constant maximum value. Since the clamping effect of the select transistors acts on each memory cell, the total maximum current of the test structure may be held below a value causing a limitation in the current generated by the entire array because of the resistance in series to the output of the test structure.