Patents by Inventor Enrico M. A. Ravanelli

Enrico M. A. Ravanelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6248639
    Abstract: A circuit protects against electrostatic discharge and includes a pad which receives an external signal source. The transistor of the present invention is connected to the circuit to be protected and includes a semiconductor body of a first conductivity type and serves as the collector of the transistor and is connected to the pad. A first doped region of a second conductivity type is contained in the semiconductor body and serves as the base of the transistor and forms a collector-to-base junction surface with the semiconductor body. A second doped region of the first conductivity type is contained in the first doped region and serves as the emitter of the transistor and forms a base-to-emitter junction surface with the first doped region. The first and second doped regions are electrically connected for establishing a shorted connection between the base and emitter.
    Type: Grant
    Filed: April 9, 1999
    Date of Patent: June 19, 2001
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Enrico M. A. Ravanelli
  • Patent number: 6147852
    Abstract: An electrostatic discharge protection circuit for integration into an integrated circuit device. The protection circuit includes at least one transistor having a first terminal connected to an input or output terminal of the integrated circuit device, a second terminal connected to a supply line for the integrated circuit device, and a control terminal connected to ground. In a preferred embodiment, the transistor is formed by a structure that includes a substrate of a first conductivity type, a first region of a second conductivity type, a second region of the first conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type. The third region has greater conductivity than the substrate and the fourth region has greater conductivity than the first region.
    Type: Grant
    Filed: September 23, 1998
    Date of Patent: November 14, 2000
    Assignee: STMicroelectronics S.r.l.
    Inventor: Enrico M. A. Ravanelli
  • Patent number: 6072682
    Abstract: A protection circuit for a power supply line in a semiconductor device, comprising first and second field-effect transistors, both transistors having their respective drain terminals connected to the power supply line. The gate source terminals of the first transistor are connected to ground through first and second resistors, respectively. The gate and source terminals of the second transistor are connected to the source terminal of the first transistor and to ground, respectively.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: June 6, 2000
    Assignee: STMicroelectronics S.r.l.
    Inventors: Enrico M. A. Ravanelli, Luca Fontanella
  • Patent number: 6064556
    Abstract: A protection circuit for a pulse type power supply line of an integrated circuit device. The protection circuit includes a switching circuit having a preset delay, and a first transistor that is connected between the pulse power supply line and ground. The gate terminal of the first transistor is coupled to ground through a first resistor, and to a second power supply line for a low DC voltage through the switching circuit. In a preferred embodiment, the switching circuit includes a second transistor that is connected between the gate terminal of the first transistor and ground. The gate terminal of the second transistor is coupled to the second power supply line through a current generator, and is also coupled to ground through a resistive element and a capacitive element that are connected in parallel.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: May 16, 2000
    Assignee: STMicroelectronics S.r.l.
    Inventor: Enrico M. A. Ravanelli
  • Patent number: 5936284
    Abstract: A circuit protects against electrostatic discharge and includes a transistor connected to the circuit to be protected. A semiconductor body of a first conductivity type serves as the collector. A first doped region of a second conductivity type is contained in the semiconductor body and serves as the base. A second doped region of the first conductivity type is contained in the first doped region and serves as the emitter. The first doped region includes a generally H-shaped doped region and a generally ring-shaped doped region forming an opening in which the second doped region serving as the emitter is received. The H-shaped doped region has a deeper junction surface than the junction surface of the ring-shaped doped region, and a dopant concentration that is less than the dopant concentration of the ring-shaped doped region. The H-shaped doped region achieves a low collector-to-base breakdown voltage and the ring-shaped doped region achieves a low snap-back voltage.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: August 10, 1999
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Enrico M. A. Ravanelli
  • Patent number: 5602914
    Abstract: Device for limiting the working voltage for mechanical switches in telephony includes terminals for connection to a telephone line, a connection and power supply branch for a control circuit extending from a first terminal, the branch having a first switch, the cathode terminal of a first Zener diode and the source terminal of a first MOSFET transistor being connected to the output terminal of the first switch, the gate terminal of the first MOSFET transistor being connected, through the anode terminal of the Zener diode, to the first terminal. The current absorbed by the device may be adjusted.
    Type: Grant
    Filed: August 1, 1995
    Date of Patent: February 11, 1997
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Antonio Andreini, Pietro Consiglio, Pietro Erratico, Enrico M. A. Ravanelli
  • Patent number: 5595921
    Abstract: The breakdown characteristics of a lateral transistor integrated in an epitaxial layer of a first type of conductivity grown on a substrate of an opposite type of conductivity and comprising a drain region formed in said epitaxial layer, are markedly improved without recurring to critical adjustments of physical parameters of the integrated structure by forming a buried region having the same type of conductivity of the substrate and a slightly higher level of doping at the interface between the epitaxial layer and the substrate in a zone laying beneath the drain region of the transistor.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: January 21, 1997
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Flavio Villa, Enrico M. A. Ravanelli
  • Patent number: 5583365
    Abstract: The breakdown characteristics of a lateral transistor integrated in an epitaxial layer of a first type of conductivity grown on a substrate of an opposite type of conductivity and comprising a drain region formed in said epitaxial layer, are markedly improved without recurring to critical adjustments of physical parameters of the integrated structure by forming a buried region having the same type of conductivity of the substrate and a slightly higher level of doping at the interface between the epitaxial layer and the substrate in a zone laying beneath the drain region of the transistor.
    Type: Grant
    Filed: February 23, 1994
    Date of Patent: December 10, 1996
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Flavio Villa, Enrico M. A. Ravanelli
  • Patent number: 5496761
    Abstract: An integrated device includes isolating regions of a first type of conductivity, each surrounding an epitaxial pocket of an opposite type of conductivity, and housing drain and source regions, and covered with an oxide layer housing gate regions and over which extend the source, drain and gate connections. For linearizing potential distribution at the epitaxial pocket--isolating region junction and close to the source regions beneath the connections, these regions are provided with a double chain of condensers embedded in the oxide layer and the terminal elements and the intermediate element of which are biased to predetermined potentials.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: March 5, 1996
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Enrico M. A. Ravanelli, Flavio Villa
  • Patent number: 5448636
    Abstract: Device for limiting the working voltage for mechanical switches in telephony includes terminals for connection to a telephone line, a connection and power supply branch for a control circuit extending from a first terminal, the branch having a first switch, the cathode terminal of a first Zener diode and the source terminal of a first MOSFET transistor being connected to the output terminal of the first switch, the gate terminal of the first MOSFET transistor being connected, through the anode terminal of the Zener diode, to the first terminal. The current absorbed by the device may be adjusted.
    Type: Grant
    Filed: February 16, 1993
    Date of Patent: September 5, 1995
    Assignee: SGS-Thomson Microelectronics S.R.L.
    Inventors: Antonio Andreini, Pietro Consiglio, Pietro Erratico, Enrico M. A. Ravanelli
  • Patent number: 5434445
    Abstract: An integrated device includes isolating regions of a first type of conductivity, each surrounding an epitaxial pocket of an opposite type of conductivity, and housing drain and source regions, and covered with an oxide layer housing gate regions and over which extend the source, drain and gate connections. For linearizing potential distribution at the epitaxial pocket-isolating region junction and close to the source regions beneath the connections, these regions are provided with a double chain of condensers embedded in the oxide layer and the terminal elements and the intermediate element of which are biased to predetermined potentials.
    Type: Grant
    Filed: April 15, 1993
    Date of Patent: July 18, 1995
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Enrico M. A. Ravanelli, Flavio Villa