Patents by Inventor Enrico Maria Ravanelli

Enrico Maria Ravanelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for suppressing parasitic effects in a junction-isolation integrated circuit
    Patent number: 6248616
    Abstract: A suppression method is applied to an integrated circuit formed on a substrate of p-type material having at least one region of n-type material with junction isolation, a first electrical contact on the frontal surface of the substrate, a second electrical contact on the n-type region and a third electrical contact on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact is taken to the potential of the second contact, otherwise they are held at the (ground) potential of the reference terminal. A device and an integrated circuit which utilize the method are also described.
    Type: Grant
    Filed: January 26, 2000
    Date of Patent: June 19, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Enrico Maria Ravanelli, Massimo Pozzoni, Giorgio Pedrazzini, Giulio Ricotti
  • Method and device for suppressing parasitic effects in a junction-isolation integrated circuit
    Patent number: 6060758
    Abstract: A suppression method is applied to an integrated circuit formed on a substrate of p-type material having at least one region of n-type material with junction isolation, a first electrical contact on the frontal surface of the substrate, a second electrical contact on the n-type region and a third electrical contact on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact is taken to the potential of the second contact, otherwise they are held at the (ground) potential of the reference terminal. A device and an integrated circuit which utilize the method are also described.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: May 9, 2000
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Enrico Maria Ravanelli, Massimo Pozzoni, Giorgio Pedrazzini, Giulio Ricotti