Abstract: A method of testing a DMOS power transistor that includes arranging a switch between low-voltage circuitry and the gate terminal of the DMOS power transistor, maintaining the switch in an open condition, applying a stress voltage to the gate terminal, testing the functionality of the DMOS power transistor, and, if the test has a positive outcome, short-circuiting the switch through zapping by fusing a normally-open fusible link. An integrated circuit device with DMOS transistor is provided that includes a gate terminal of the DMOS transistor coupled to a control element, a normally-open switch element coupled in series between the gate terminal and the control element and including two metallic regions with an insulating between them connected in parallel with the switch element and in series between the gate terminal and the control element.

Abstract: A circuit for temperature compensating the inverse saturation current of a bipolar transistor having a collector region, base and emitter regions defining a base-emitter junction is disclosed. A diode element having substantially said same saturation current is parallel-connected in reverse configuration to said base-emitter junction of the bipolar transistor. If the bipolar transistor is NPN type, the diode has an anode and cathode connected respective to the emitter and base regions of the transistor.