Abstract: A fuzzy processor with an improved architecture. The fuzzy processor includes a fuzzy rule processor, an internal fuzzy instruction memory, an internal knowledge base memory, an arithmetic-logic unit, a control unit that can execute non-fuzzy instructions that are typical of conventional microprocessors, and an internal memory for storing the non-fuzzy instructions. The improved fuzzy processor architecture has an ability to load other knowledge bases and other fuzzy rules from outside the processor concurrently and transparently with respect to instruction processing. The processor can also process both fuzzy instructions and non-fuzzy instructions, can perform conditional and unconditional jumps within a set of fuzzy rules that are being processed, and can conditionally swap the knowledge base or the set of rules that are to be processed.

Abstract: A processor operating in a fizzy logic's mode and including a fuzzyfication unit receiving a plurality of input variables on its input and being adapted to compute a membership value of such variables in a membership function, a processing unit connected downstream of the fuzzyfication unit to produce a fuzzy set, i.e. the results of fuzzy logic inference operations performed on the plurality of variables, and a defuzzyfication unit operative to translate the inference results into a so-called crisp value. The processor further includes a first memory device connected to the fuzzyfication unit and containing the set of membership functions, a second memory device connected to the defuzzyfication unit and containing the set of crisp value which appear in the THEN part of the fizzy rules, and a further memory device connected to the defuzzyfication unit.