Abstract: In one embodiment, an apparatus includes a first block configured to decompose an input signal into a positive component and a negative component. The apparatus further includes a second block configured to generate a mixer positive driver component from the positive component and a mixer negative driver component from the negative component and input the mixer positive driver component and the negative driver component into a mixer for a wireless transmitter.

Abstract: A circuit including a current source, an inverter, and a device. The current source is configured to receive a first reference voltage and supply an output current. The inverter has a transconductance. The inverter includes a first transistor having a source and a drain and a second transistor having a source. The source of the first transistor is connected to the current source. The source of the first transistor is configured to receive a portion of the output current. The source of the second transistor is connected to the drain of the first transistor. The device is configured to select the first reference voltage such that the output current of the current source varies with changes in a temperature of the current source to maintain the transconductance of the inverter at a same value and prevent changes in respective transition frequencies of both the first transistor and the second transistor.

Abstract: In one embodiment, a voltage controlled oscillator (VCO) is provided. The VCO includes a tank circuit. Also, the VCO includes a first pair of transistors. The drains of the first pair of transistors are coupled to the tank circuit and the gates of the first pair of transistors are cross-coupled with the drains of the first pair of transistors. The first pair of transistors each have a first threshold voltage. The VCO further includes a second pair of transistors. The drains of the second pair of transistors are respectively coupled to the sources of the first pair of transistors and the gates of the second pair of transistors are respectively coupled to the gates of the first pair of transistors, The second pair of transistors each have a second threshold voltage higher than the first threshold voltage.

Abstract: A circuit including a current source, an inverter, and a device. The current source is configured to receive a first reference voltage and supply an output current. The inverter has a transconductance. The inverter includes a first transistor having a source and a drain and a second transistor having a source. The source of the first transistor is connected to the current source. The source of the first transistor is configured to receive a portion of the output current. The source of the second transistor is connected to the drain of the first transistor. The device is configured to select the first reference voltage such that the output current of the current source varies with changes in a temperature of the current source to maintain the transconductance of the inverter at a same value and prevent changes in respective transition frequencies of both the first transistor and the second transistor.

Abstract: The transition frequency of an inverter can vary with the transconductance of its internal transistors as a function of temperature and bias level. To maintain consistent transition frequency across temperatures, and therefore reduce the phase noise variation introduced by the inverter, systems, methods, and circuits are disclosed for biasing the inverter with a temperature varying current such that the transconductance of transistors remains constant across temperatures, while maintaining the lowest possible power consumption to do so. Various embodiments can include using current sources that have proportional-to-absolute-temperature (PTAT) devices.

Abstract: The transition frequency of an inverter can vary with the transconductance of its internal transistors as a function of temperature and bias level. To maintain consistent transition frequency across temperatures, and therefore reduce the phase noise variation introduced by the inverter, systems, methods, and circuits are disclosed for biasing the inverter with a temperature varying current such that the transconductance of transistors remains constant across temperatures, while maintaining the lowest possible power consumption to do so. Various embodiments can include using current sources that have proportional-to-absolute-temperature (PTAT) devices.

Abstract: In one embodiment, a voltage controlled oscillator (VCO) is provided. The VCO includes a tank circuit. Also, the VCO includes a first pair of transistors. The drains of the first pair of transistors are coupled to the tank circuit and the gates of the first pair of transistors are cross-coupled with the drains of the first pair of transistors. The first pair of transistors each have a first threshold voltage. The VCO further includes a second pair of transistors. The drains of the second pair of transistors are respectively coupled to the sources of the first pair of transistors and the gates of the second pair of transistors are respectively coupled to the gates of the first pair of transistors, The second pair of transistors each have a second threshold voltage higher than the first threshold voltage.

Abstract: The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45° with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.

Abstract: The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45° with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.

Abstract: The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45° with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.

Abstract: The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45° with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.