Patents by Inventor Enrico Scian

Enrico Scian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6236244
    Abstract: The invention relates to an electronic level shifter circuit for driving a high-voltage output stage. This output stage comprises a complementary pair of transistors connected between first and second supply voltage references, and at least one PMOS pull-up transistor connected in series with an NMOS pull-down transistor. An additional transistor is connected in parallel with the pull-up transistor, and the driver circuit has a first output connected to the control terminal of the pull-up transistor and a second output connected to the control terminal of the additional transistor.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: May 22, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Riccardo Depetro, Fabrizio Martignoni, Enrico Scian
  • Patent number: 6194948
    Abstract: A method, and related circuit, prevent the triggering of a parasitic transistor in an output stage of an electronic circuit. The stage includes a transistor pair with at least one transistor of the pull-up PMOS type having respective source, gate and drain terminals and a body terminal, and a parasitic bipolar transistor having a terminal connected to the body terminal. The method includes the steps of providing a capacitor connected between the body and source terminals of the PMOS transistor; and using a control circuit to suppress the body effect of the pull-up PMOS transistor.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: February 27, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Enrico Scian, Fabrizio Martignoni, Riccardo Depetro
  • Patent number: 6184716
    Abstract: The invention relates to a high-voltage final output stage for driving an electric load, of the type which comprises a complementary pair of transistors connected between first and second supply voltage references, and at least one PMOS pull-up transistor connected in series with an NMOS pull-down transistor. The stage comprises an additional PMOS transistor connected in parallel with the pull-up transistor and having the body terminal in common therewith. More particularly, the body terminals of both PMOS transistors are formed in the semiconductor within a common well which can withstand high voltages, and the additional transistor is a thick oxide PMOS power transistor.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: February 6, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Riccardo Depetro, Fabrizio Martignoni, Enrico Scian