Patents by Inventor Enrico Varesi
Enrico Varesi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220384722Abstract: Methods, systems, and devices for a memory device with laterally formed memory cells are described. A material stack that includes a conductive layer between multiple dielectric layers may be formed, where the conductive layer and dielectric layers may form a channel in a sidewall of the material stack. The channel may be filled with one or more materials, where a first side of an outermost material of the one or more materials may be exposed. An opening may be formed in the material stack that exposes a second side of at least one material of the one or more materials. The opening may be used to replace a portion of the at least one material with a chalcogenide material where the electrode materials may be formed before replacing the portion of the at least one material with the chalcogenide material.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Inventors: Thomas M. Graettinger, Lorenzo Fratin, Patrick M. Flynn, Enrico Varesi, Paolo Fantini
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Publication number: 20220384720Abstract: Methods, systems, and devices for techniques for memory cells with sidewall and bulk regions in planar structures are described. A memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. A conductive path between the first electrode and the second electrode may extend in a direction away from a plane defined by a substrate. The self-selecting storage element may include a bulk region and a sidewall region. The bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. The bulk region and sidewall region may extend between the first electrode and the second electrode and in the direction away from the plane defined by the substrate.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Inventors: Lorenzo Fratin, Enrico Varesi, Paolo Fantini
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Publication number: 20220384719Abstract: Methods, systems, and devices for techniques for memory cells with sidewall and bulk regions in vertical structures are described. A memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. The bulk region may extend between the first electrode and the sidewall region. The bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. Also, the sidewall region may separate the bulk region from the second electrode.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Inventors: Lorenzo Fratin, Enrico Varesi, Paolo Fantini
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Publication number: 20220336005Abstract: Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Two word line plates in a same plane may be activated via a shared electrode. Memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.Type: ApplicationFiled: April 15, 2021Publication date: October 20, 2022Inventors: Paolo Fantini, Enrico Varesi, Lorenzo Fratin, Fabio Pellizzer
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Publication number: 20220335997Abstract: Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Memory cells coupled with a word line plate, or a subset thereof, may represent a logical page for accessing memory cells. Each word line plate may be coupled with a corresponding word line driver via a respective electrode. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.Type: ApplicationFiled: April 15, 2021Publication date: October 20, 2022Inventors: Paolo Fantini, Lorenzo Fratin, Fabio Pellizzer, Enrico Varesi
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Publication number: 20220208602Abstract: Architectures of 3D memory arrays, systems, and methods regarding the same are described. An array may include a substrate arranged with conductive contacts in a geometric pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, a sacrificial layer may be deposited in a trench that forms a serpentine shape. Portions of the sacrificial layer may be removed to form openings, into which cell material is deposited. An insulative material may be formed in contact with the sacrificial layer. The conductive pillars extend substantially perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. A chalcogenide material may be formed in the recesses partially around the conductive pillars.Type: ApplicationFiled: January 11, 2022Publication date: June 30, 2022Inventors: Lorenzo Fratin, Enrico Varesi, Paolo Fantini
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Patent number: 11264568Abstract: The present disclosure includes textured memory cell structures and method of forming the same. In one or more embodiments, a memory cell includes a buffer portion formed on an amorphous portion and an active portion formed on the buffer portion, wherein the active portion is textured with a single out of plane orientation.Type: GrantFiled: July 29, 2016Date of Patent: March 1, 2022Assignee: Micron Technology, Inc.Inventors: Andrea Redaelli, Mattia Boniardi, Enrico Varesi, Raffaella Calarco, Jos E. Boschker
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Patent number: 11244855Abstract: Architectures of 3D memory arrays, systems, and methods regarding the same are described. An array may include a substrate arranged with conductive contacts in a geometric pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, a sacrificial layer may be deposited in a trench that forms a serpentine shape. Portions of the sacrificial layer may be removed to form openings, into which cell material is deposited. An insulative material may be formed in contact with the sacrificial layer. The conductive pillars extend substantially perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. A chalcogenide material may be formed in the recesses partially around the conductive pillars.Type: GrantFiled: May 3, 2019Date of Patent: February 8, 2022Inventors: Lorenzo Fratin, Enrico Varesi, Paolo Fantini
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Patent number: 11152427Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A memory device, such as a selector device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. A selector device, for instance, may have a composition of selenium, arsenic, and at least one of boron, aluminum, gallium, indium, or thallium. The selector device may also be composed of germanium or silicon, or both. The relative amount of boron, aluminum, gallium, indium, or thallium may affect a threshold voltage of a memory component, and the relative amount may be selected accordingly. A memory component may, for instance have a composition that includes selenium, arsenic, and some combination of germanium, silicon, and at least one of boron, aluminum, gallium, indium, or thallium.Type: GrantFiled: August 19, 2019Date of Patent: October 19, 2021Assignee: Micron Technology, Inc.Inventors: Paolo Fantini, F. Daniel Gealy, Enrico Varesi, Swapnil A. Lengade
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Patent number: 11114615Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A component of a memory cell, such as a selector device, storage device, or self-selecting memory device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. The chalcogenide material, for instance, may have a composition of selenium, germanium, and at least one of boron, aluminum, gallium, indium, or thallium. The chalcogenide material may in some cases also include arsenic, but may in some cases lack arsenic.Type: GrantFiled: June 18, 2020Date of Patent: September 7, 2021Assignee: Micron Technology, Inc.Inventors: Enrico Varesi, Paolo Fantini, Lorenzo Fratin, Swapnil A. Lengade
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Patent number: 11094879Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element.Type: GrantFiled: September 4, 2018Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventors: Andrea Gotti, F. Daniel Gealy, Innocenzo Tortorelli, Enrico Varesi
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Publication number: 20210249598Abstract: Methods, systems, and devices for composite electrode material chemistry are described. A memory device may include an access line, a storage element comprising chalcogenide, and an electrode coupled with the memory element and the access line. The electrode may be made of a composition of a first material doped with a second material. The second material may include a tantalum-carbon compound. In some cases, the second may be operable to be chemically inert with the storage element. The second material may include a thermally stable electrical resistivity and a lower resistance to signals communicated between the access line and the storage element across a range of operating temperatures of the storage element as compared with a resistance of the first material.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Inventors: Pengyuan Zheng, Enrico Varesi, Lorenzo Fratin, Dale Collins, Yongjun J. Hu
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Patent number: 10892406Abstract: A phase change memory (PCM) cell can include a PCM layer. A first electrode and a second electrode disposed on opposite sides of the PCM layer. The first electrode, the second electrode, or both includes a metal ceramic composite material layer disposed between an upper barrier layer and a lower barrier layer and wherein the metal ceramic composite material layer provides a corresponding electrode with an electrical resistivity of from 10 mOhm-cm to 1000 mOhm-cm.Type: GrantFiled: June 4, 2018Date of Patent: January 12, 2021Assignee: Intel CorporationInventors: Stephen Russell, Andrea Gotti, Andrea Redaelli, Enrico Varesi, Innocenzo Tortorelli, Lorenzo Fratin, Alessandro Sebastiani
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Patent number: 10884640Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.Type: GrantFiled: April 2, 2019Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
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Publication number: 20200350203Abstract: Architectures of 3D memory arrays, systems, and methods regarding the same are described. An array may include a substrate arranged with conductive contacts in a geometric pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, a sacrificial layer may be deposited in a trench that forms a serpentine shape. Portions of the sacrificial layer may be removed to form openings, into which cell material is deposited. An insulative material may be formed in contact with the sacrificial layer. The conductive pillars extend substantially perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. A chalcogenide material may be formed in the recesses partially around the conductive pillars.Type: ApplicationFiled: May 3, 2019Publication date: November 5, 2020Inventors: Lorenzo Fratin, Enrico Varesi, Paolo Fantini
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Publication number: 20200321523Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A component of a memory cell, such as a selector device, storage device, or self-selecting memory device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. The chalcogenide material, for instance, may have a composition of selenium, germanium, and at least one of boron, aluminum, gallium, indium, or thallium. The chalcogenide material may in some cases also include arsenic, but may in some cases lack arsenic.Type: ApplicationFiled: June 18, 2020Publication date: October 8, 2020Inventors: Enrico Varesi, Paolo Fantini, Lorenzo Fratin, Swapnil A. Lengade
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Patent number: 10727405Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A component of a memory cell, such as a selector device, storage device, or self-selecting memory device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. The chalcogenide material, for instance, may have a composition of selenium, germanium, and at least one of boron, aluminum, gallium, indium, or thallium. The chalcogenide material may in some cases also include arsenic, but may in some cases lack arsenic.Type: GrantFiled: December 20, 2018Date of Patent: July 28, 2020Assignee: Micron Technology, Inc.Inventors: Enrico Varesi, Paolo Fantini, Lorenzo Fratin, Swapnil A. Lengade
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Patent number: 10553792Abstract: The present disclosure includes textured memory cell structures and method of forming the same. In one or more embodiments, a memory cell includes a buffer portion formed on an amorphous portion and an active portion formed on the buffer portion, wherein the active portion is textured with a single out of plane orientation.Type: GrantFiled: December 14, 2017Date of Patent: February 4, 2020Assignee: Micron Technology, Inc.Inventors: Andrea Redaelli, Mattia Boniardi, Enrico Varesi, Raffaella Calarco, Jos E. Boschker
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Publication number: 20200035753Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A memory device, such as a selector device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. A selector device, for instance, may have a composition of selenium, arsenic, and at least one of boron, aluminum, gallium, indium, or thallium. The selector device may also be composed of germanium or silicon, or both. The relative amount of boron, aluminum, gallium, indium, or thallium may affect a threshold voltage of a memory component, and the relative amount may be selected accordingly. A memory component may, for instance have a composition that includes selenium, arsenic, and some combination of germanium, silicon, and at least one of boron, aluminum, gallium, indium, or thallium.Type: ApplicationFiled: August 19, 2019Publication date: January 30, 2020Inventors: Paolo Fantini, F. Daniel Gealy, Enrico Varesi, Swapril A. Lengade
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Publication number: 20190324671Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.Type: ApplicationFiled: April 2, 2019Publication date: October 24, 2019Applicant: Intel CorporationInventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi