Abstract: A telephone switch in which communication between tasks controlling the switch hardware and the timing of those tasks, including the timing of repeating tasks, is controlled through a mail system in which mail messages are sent between tasks that may be running on separate microprocessors. The mail messages specify the destination task, the function that the task is to perform and any desired delay before the mail is to be delivered to the destination task. Repeating tasks send mail to themselves each time they repeat, specifying in the mail message the task to be repeated and the desired delay interval. A mail task holds the mail for the specified delay interval before it is delivered, and receipt of a mail message causes the task to run.

Abstract: A processor apparatus which is capable of performing floating point arithmetic. The processor apparatus includes a plurality of individual processing cells which are interconnected from left to right in a chain so that any of the processor cells can operate to receive a bit of any slice in a digital word. Each cell includes a memory which essentially is coupled via a multiplexer to an arithmetic logic unit, a controllable multiplier quotient store, a controllable loop path, and controllable status path device. Each of these devices are under control of a control mechanism which is included in the cell, and therefore each path can be connected to any other path via various multiplexers utilized in the circuitry. Essentially, each cell includes a multiport RAM, programmable logic arrays which implement the control logic plus path logic which provides the communication between neighboring cells.