Abstract: According to an embodiment, a capacitance determination circuit is provided comprising a voltage controlled oscillator configured to generate a frequency signal whose frequency depends on a control voltage supplied to the voltage controlled oscillator, a capacitor coupled to the voltage controlled oscillator wherein the control voltage depends on a voltage across the capacitor and a processing circuit configured to generate, based on the frequency signal generated by the voltage controlled oscillator over a time interval comprising at least one phase in which the capacitor is charged and comprising at least one phase in which the capacitor is discharged, an indication of the capacitance of the capacitor.

Abstract: According to various embodiments, a multi-slope converter can have the following: an integrator circuit having a charge store; a clocked comparator; a sensor circuit having a capacitor arrangement and a charging circuit for pre-charging the capacitor arrangement, a discharging circuit; a switch arrangement and a controller circuit for actuating the switch arrangement based on a clock signal; wherein the controller circuit is set up to actuate the switch arrangement such that, alternately: in an integration cycle electrical charge is transferred from the capacitor arrangement of the sensor circuit to the charge store of the integrator circuit, and in a deintegration cycle the charge store of the integrator circuit is discharged by means of the discharging circuit, wherein after the integration cycle a residual charge remains stored in the charge store of the integrator circuit and is taken into consideration during a subsequent integration cycle.

Abstract: According to various embodiments, a multi-slope converter can have the following: an integrator circuit having a charge store; a clocked comparator; a sensor circuit having a capacitor arrangement and a charging circuit for pre-charging the capacitor arrangement, a discharging circuit; a switch arrangement and a controller circuit for actuating the switch arrangement based on a clock signal; wherein the controller circuit is set up to actuate the switch arrangement such that, alternately: in an integration cycle electrical charge is transferred from the capacitor arrangement of the sensor circuit to the charge store of the integrator circuit, and in a deintegration cycle the charge store of the integrator circuit is discharged by means of the discharging circuit, wherein after the integration cycle a residual charge remains stored in the charge store of the integrator circuit and is taken into consideration during a subsequent integration cycle.

Abstract: The disclosure is directed to low-power high-resolution analog-to-digital converter (ADCs) circuits implemented with a delta-sigma modulators (DSMs). The DSM includes a single-bit, self-oscillating digital to analog converter (SB-DAC) and a dual-slope integrating quantizer that may replace an N-bit quantizer found in a conventional DSM. The integrating quantizer of this disclosure oscillates after quantization because the SB-DAC in the feedback path directly closes the DSM loop. The integrating quantizer circuit includes a switch at the input and two phases per sample cycle. During the first phase the switch sends an input analog signal to an integrator. During the second phase, the switch sends the feedback signal from the output of the self-oscillating SB-DAC to the integrator. The input to the SB-DAC may be output from a clocked comparator.

Abstract: According to an embodiment, a capacitance determination circuit is provided comprising a voltage controlled oscillator configured to generate a frequency signal whose frequency depends on a control voltage supplied to the voltage controlled oscillator, a capacitor coupled to the voltage controlled oscillator wherein the control voltage depends on a voltage across the capacitor and a processing circuit configured to generate, based on the frequency signal generated by the voltage controlled oscillator over a time interval comprising at least one phase in which the capacitor is charged and comprising at least one phase in which the capacitor is discharged, an indication of the capacitance of the capacitor.