Patents by Inventor Enrique Quique Garcia

Enrique Quique Garcia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5737240
    Abstract: A mailbox message system is coupled between a processor having a mailbox and one or more peripheral devices or circuits communicating information to the processor. The mailbox message system in the present invention reports events which occur in the peripheral devices or circuits to the mailbox within the processor to be serviced by the processor. The mailbox message system receives inputs from the processor indicating which events are allowed to be currently serviced by the processor and stores these inputs in a first memory. The mailbox message system further receives unique signals representing distinct events from the peripheral devices and stores these signals in a second memory. The generated events which are pending service in the second memory are then compared with the allowed events in the first memory. When a match exists, a message is encoded and transmitted to the mailbox of the processor indicating that the processor has an event to be serviced.
    Type: Grant
    Filed: January 25, 1996
    Date of Patent: April 7, 1998
    Assignee: International Business Machines Corporation
    Inventors: Earle Ellsworth, Laura Hepner Evans, Sangram Singh Ghoman, Enrique Quique Garcia, Thomas Charles Jarvis, Matthew Joseph Kalos, Ralph O'Neill, Lisa Phan, David Brent Schreiber
  • Patent number: 5644583
    Abstract: A soft error correction technique and system for an odd weight row error correction code comprising a memory for storing a data word and its associated check bits and a control circuit for reading and inverting the data word and the check bit stored in memory. The system also comprises an inversion circuit for selectively reinverting the check bits. In a specific implementation, the check bit inversion circuit includes a plurality of Exclusive Or gates. A first input of each Exclusive Or gate is connected to receive the check bit from memory and a second input is connected to receive a control bit from a central processing unit via a software accessible control register. The inverted data word and the selectively reinverted check bit are input to an odd weight row error correcting circuit to correct a detected bit error. A method for correcting data errors for an odd weight row error correction system is also provided.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 1, 1997
    Assignee: International Business Machines Corporation
    Inventors: Enrique Quique Garcia, Sushama Mahesh Paranjape